IBIS Models for Signal Integrity Applications

Bob Ross, Interconnectix, Inc., Chair. Syed Huq, National Semiconductor Corp., Vice-Chair. Jon Powell, Quad Design, Inc., Librarian EIA IBIS Open Forum Committee Electrical Engineering Times, A CMP Publication September 2, 1996

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The Need

EDA vendors, semiconductor vendors and system designers need closer alliance to support advancing product speeds and complexities. In the early 1990s, while attempting to convey the stringent requirements of PCI bus drivers, Intel recognized the need to model the analog timing and strength characteristics of I/O buffers. Intel based models on I/V tables for a behavioral simulator and I/V behavioral templates for a Spice simulator. The simulation results correlated well for rigorous signal integrity analysis and characterization of the PCI bus.

Data preparation for models and model availability became primary issues. Rather than relying on the availability of vendor specific model formats, Intel invited other EDA vendors to join forces and define a common model format. What emerged is referred to as IBIS (I/O Buffer Information Specification) Version 1.0 in June 1993 and a clarification update Version 1.1 in August 1993. What also evolved is the IBIS Open Forum dedicated to keeping abreast with technical needs and promoting the availability of IBIS models.


Spice simulation remains a primary method for analysis and design. It is particularly useful in validating new component performance and new layout schemes. Basing models on Spice is a theoretical possibility. However, such an approach suffers from some practical realities: different Spice simulators, different formats, undocumented simplifications, different options, simulation speed, simulation convergence, and model availability.

The user is saddled with resolving these issues. Getting the best models often clashes with the need for the semiconductor vendors to protect their proprietary process and architecture investment. Thus, Spice-based models have become the weak link as design complexity increases and EDA tools evolve in sophistication and capability.

Like Spice Models, IBIS models are formatted in human-readable, ASCII text. However, IBIS models do not require proprietary information. The critical electrical characteristics are based on derivative information -- derived by simulation or measurement. Consequently, models of current devices are becoming more readily available in IBIS than in Spice formats.

Spice models tend to be single buffer centric; the model often represents one of several inputs or outputs of a buffer. IBIS models are component centric; the model describes all pins of the physical component. Physical data bases used for large board designs provide suitable component footprint interfaces, ideal for the insertion of IBIS component models. Thus, EDA vendors support IBIS to integrate electrical components with physical data describing thousands of nets. At least 17 EDA vendor products around the world support some form of IBIS -- directly or through translation into internal data bases and formats.


IBIS Version 1.1

Version 1.1 of IBIS provided a baseline architecture for supporting current CMOS, BiCMOS, and TTL technologies. Its electrical characteristics contain I/V tables, switching information and package information (Fig. 1).

Figure 1. IBIS Version 1.1 Electrical I/O Buffer

Blocks 1 and 2 represent the pulldown and pullup transistors of a standard TTL, BiCMOS or CMOS I/O buffer outputs stage. DC I/V tables behaviorally describe these buffers.

Block 3 also consists of DC I/V tables representing the ESD or clamping diodes. When present, these diodes clamp transmission line reflections.

Block 4 shows the transition time of the output as it switches from one logic state to another. Rise and fall times are represented separately as non-reduced ratios of transition voltage to transition time: dV/dt.

Block 5 represents the pad and package parasitics seen by the output buffer. C_comp is the total output capacitance due to the output pad, clamp diodes and (for I/O structures) input transistors. L_pkg, R_pkg and C_pkg are the inductance, resistance and capacitance of the bond wire and pin combination of the package.

Models of just input pins need only Blocks 3 and 5.

These electrical characteristics are derived under defined test conditions from Spice model simulations or from device measurements. Spice models often contain process variations and allow simulations under temperature and supply extremes. The IBIS format groups corner descriptions into three columns: ˘typ÷ (typical), ˘min÷ (weak, slow) and ˘max÷ (strong, fast). These corners are defined with respect to process, temperature and supply variations.

The IBIS format adds these elements that are not included in Spice models:

Pin classifications for each pin in a component as Input, Output, 3-state, I/O, Open_drain, Power, Gnd, NC, and more in Version 2.1.

Specification information (thresholds Vinh and Vinl) with more in Version 2.1 useful for automated timing and signal integrity evaluation of nets.

Version 2.1 (ANSI/EIA-656)

IBIS Open Forum activity continued, leading to the ratification of IBIS Version 2.0 in June 1994. In February 1995, the Open Forum formally affiliated with the Electronic Industries Association (EIA) and pursued minor technical modifications and textual clarifications. This eventually led to Version 2.1. Through formal letter ballot review processes, IBIS became an American National Standard ANSI/EIA-656 in December 1995. Version 2.1 has remained as the next stable level of functionality. The US Technical Advisory Group (TAG) for IEC Technical Committee 93 has forwarded it as a work item for international standardization.

Briefly, Version 2.1 contains all of the Version 1.1 features and adds functionality required for other existing technologies. Such functionality includes support for devices with more than one supply voltage, ECL devices, discrete terminators, differential I/O, coupling between package pins, and timing load specification. Version 2.1 also adds switching waveform tables consisting of voltage versus time data (V/T tables). These tables extend the electrical detail by describing buffers with controlled rise and fall times, or buffers whose output waveforms are significantly non-linear. Thus, Version 2.1 supports backward compatibility with Version 1.1 models and also supports common configurations such as ECL and PECL differential clock drivers, GTL I/O structures, and line drivers with two voltage rails.

Version 3.0 and Beyond

Currently, the EIA IBIS Open Forum Committee is developing IBIS Version 3.0. Enhancements considered include: support for increasingly complex packages such as found in SIMM modules, MCMs, and connectors, diode transit time modeling details, internal multi-staged driver architecture, model selection and more specification detail. Version 3.0 is targeted for approval by the end of 1996. Full backward compatibility will still be maintained.

Broad Based Open Forum Support

The EIA IBIS Open Forum Committee continues with active participation. Telephone conference call meetings are conducted every third week with EDA and semiconductor vendors and system designers. Two face-to-face meetings are scheduled in conjunction with the Design Automation Conference and the Design SuperCon show. In 1996 alone, over 65 people representing over 35 companies have participated. More than 20 companies hold formal membership status.

IBIS Model Tools

The IBIS Open Forum Committee has funded the development of the ibis_chk utilities for Version 1.1 and Version 2.1. These utilities check for correct IBIS model format. They can also function as IBIS parser and translator front ends. The executables are publicly available at no charge.

North Carolina State University under ARPA funding and with EDA vendor participation has generated some public domain Spice to IBIS translators and a utility for viewing IBIS files. These can be used directly or can be adapted to specific semiconductor vendor Spice formats. The source code and executables are available at no charge.

HyperLynx offers at no charge their Visual IBIS Editor for viewing, checking and editing IBIS files at the Version 1.1 and Version 2.1 levels. Many other companies provide their own IBIS development, viewing, and translation tools and products.

Models and Websites

The IBIS Open Forum Committee supplies information and development tools and promotes IBIS model development and distribution by all sources. The IBIS Open Forum website can be accessed under http://vhdl.org/pub/ibis. It contains the complete IBIS repository: tools (ibis_chk and Spice to IBIS utilities), models, meeting minutes, e-mail archive, working documents, issues documents (BIRD for Buffer Issue Resolution Document), rosters, contacts, and other descriptive documents (Cookbook, Overview, EDN, March 1995 article). The EIA/IBIS website is http://eia.org/eig/ibis/ibis.htm. It links to member company home pages and links to IBIS models, frequently asked questions and other IBIS related information.

The vhdl.org model repository currently contains IBIS models from Intel and National Semiconductor. Also, Intel, National Semiconductor, Motorola, VLSI Technology, and Micron Technology supply IBIS models under their own home pages -- amounting to hundreds of models available for downloading. Many other vendors offer IBIS models directly through their sales organizations or through internal contacts. Models that are posted on the vhdl.org site have been checked by ibis_chk for syntax compliance. This repository is free to any semiconductor vendor for serving as a model directory and for storing actual models.

Commercial Vendors are providing models. H.A.S. Electric is offering a growing list of over 800 IBIS models. Symmetry Design is contracting its model development services directly to semiconductor vendors. Zeelan Technology (recently acquired by Mentor Graphics Corporation) operates independently and has a large library of many thousand measurement-based models. These are simulator-specific, encrypted, behavioral models including those with IBIS-like formats that link directly into simulator databases.

Future Directions and Information

IBIS formatted models solve several problems. Semiconductor vendors can offer behavioral models in one format that all vendors can handle, rather than dividing their resources to support many formats. Semiconductor vendors can offer the best under consistent format guidelines without disclosing proprietary data. EDA vendors working with IBIS models have reported design successes and reduced time to market. Through standardization processes and design validation, the IBIS format has undergone scrutiny and is here to stay.

More documentation is emerging. Recent (1996) Micron Technology SRAM and DRAM data books and a National Semiconductor Interface data book contain informative technical sections on IBIS.

For users of EDA tools, the ball is in your court. Several large companies are forcing the issue by making IBIS model support a requirement for component purchase. We encourage this so silicon vendors face their responsibility to provide simulation models along with physical devices. Internal advocates for model availability need this customer pressure to help sway investment decisions for IBIS model production. Time to market improvements based on EDA tool advances make rapid and easy model availability a competitive business requirement. A significant beginning has occurred, but we need much more involvement.

The ANSI/EIA-656 specification is available through Global Engineering Documents, (800) 854-7179. The EIA IBIS Open Forum Committee operates using a public e-mail reflector. You may subscribe by sending your request to ibis-request@vhdl.org. You may get additional information and answers to specific questions by sending a query to ibis- info@vhdl.org. For information on joining the IBIS Committee contact Patti Rusher, (703) 907-7545, pattir@eia.org.