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Version 1.8 (Final) September 26, 1994 By Derrick Duehren, Will Hobbs, Arpad Muranyi, and Robin RosenbaumIntel Corporation

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Another option is to construct a behavioral model of the device. With this type of modeling technique, the DC I/V (current vs. voltage) curves are extracted along with the rise and fall time and packaging information and used to create a 'black box' model of the I/O buffer. There are several advantages to this technique. The required information is readily available via measurement, it is fast, and it is non- proprietary. More importantly, several CAE vendors (some examples are Interconnectix, Quad Design Technologies, and HyperLynx) supply software that is targeted specifically towards simulating hundreds of nets and drivers on a PC board and these programs require behavioral-style I/O buffer models. Unfortunately, until now there has been no standard way to either extract or format the information. A behavioral I/O buffer model created for one vendor's CAE program would, at the least, have to be reformatted for another’s. Because there was no standard format, IC vendors were reluctant to create and maintain several different behavioral models of a device.

IBIS relies on tabulated current versus voltage (I/V) characteristics, rise and fall time characteristics, and package information, thus protecting vendor intellectual property. This approach provides models that reveal no proprietary information about the design or process technology.

The behavioral IBIS simulations run much faster than any corresponding structural (e.g., silicon) models. Speed improvements of 25 times are common, yet the I/V methodology accurately takes into account many non-linear aspects of the I/O design, such as forward-biased ESD protection-diode effects and pullup and pulldown characteristics. Package parasitic can be specified at a pin-to-pin level of detail.

As market pressures shorten the design cycle, the design engineers need earlier availability of the models. At the same time, faster system designs result in more complex and less forgiving design issues. The IBIS modeling data can be derived from circuit simulation or measured on a curve tracer and oscilloscope. By using such data sources, semiconductor vendors can provide accurate I/O buffer models with or before the first component availability. In addition, any model created using the IBIS format is compatible with virtually all industry-wide simulation platforms.

IBIS was first developed at Intel Corporation and has been expanded to its current form (Version 2.0) through the cooperative efforts of over 20 additional analog simulator vendors, computer manufacturers, IC vendors, and universities. In May, 1993, this group formed itself into the IBIS Open Forum, an open, voluntary, cooperative association. The IBIS Open Forum participation increases monthly.

The IBIS Open Forum has collected no dues. The Forum meets via teleconference every third week to propose updates to the IBIS standard (Version 2.0 was ratified during the June ‘94 Design Automation Conference), to help new participants get up to speed, and to otherwise advance the standard. The Forum has also gathered in person to hold summits and ratify changes.

Most of the Forum activities are handled through EMAIL discussions using a reflector "ibis@vhdl.org". To add your name to the reflector’s distribution list, send your email address to ibis-request@vhdl.org. The process of making changes and improvements is through a "BIRD" (Buffer Issue Resolution Document) process involving consensus of participants. (Thus far, all changes have been approved by unanimous vote of the participants.)

Although there is no fee to participate, many companies have paid $500 to get the source code of an IBIS_CHK program (Golden Parser) that checks for correctness of Version 1.1 IBIS files. (An IBIS_CHK program for Version 2.0 is being created and is expected to be available Oct. ‘94). The executable code for the parser is available through vhdl.org

Even though the committee is composed of competing semiconductor vendor and EDA companies, there is an unusual amount of cooperation and candor based on a common interest of making model information available.

The Forum is currently going through a selection process to decide which standards organization to affiliate with. Formal affiliation is expected in ‘94.

Controlled slew rate devices.

ECL and PECL technologies.

Independent control over power rails so RS232 and other type of devices with multiple rails can be modeled.

Differential drivers and devices.

Open-drain I/O devices, such as open drain and open collector devices.

Expanded package model definitions to include coupling between pins.

An IBIS Golden Parser is available for checking model syntax against IBIS. This parser is also used by IBIS forum companies to create simulator-specific IBIS data model generators. The behavior of model generators based on the Golden Parser varies insignificantly between simulators. The Golden Parser is openly available in object code format for several platforms. You can also license the Golden Parser source code from the IBIS Open Forum.

For simulating I/O interconnects, participating IC vendors can offer detailed descriptions of their drivers and receivers, organized into machine-parsable ASCII files. Each such file provides the information needed for modeling all the buffers of a component.

An IC vendor can put data into an IBIS file to be used as input for a broad range of simulation packages. Such simulation packages can interpret the IBIS data either directly or using a translator from the EDA vendor. In other formats, the same data can be used under SPICE packages for behavioral elements such as voltage-controlled current sources to model the pull-up, pull-down, and clamp characteristics of a given buffer.

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Figure 1: Elements of an IBIS Model**

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**Figure 2: IBIS Behavioral Block Diagram**

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The elements of the IBIS model correspond to the keywords in the IBIS format specification:

* Element 1 contains the pull-down information, including the minimum and maximum currents for the given voltages of the pull-down. The [Pulldown] IBIS table lists voltages from -Vcc to 2*Vcc.

The wide voltage range on the output (-Vcc to 2*Vcc) is provided to improve the accuracy of certain simulators. Many simulators benefit from including these characteristics in the model. For simulators that do not extrapolate unspecified voltages, the ranges given are more than adequate.

[Pulldown]* Element 2 contains the pull-up information, modeling the characteristics of the buffer when driven high.| Voltage I(typ) I(min) I(max) -5.00V -65.55mA -51.11mA -85.99mA -4.50V -65.16mA -50.67mA -85.66mA -4.00V -64.67mA -50.20mA -85.18mA -3.50V -64.08mA -49.67mA -84.53mA -3.00V -63.41mA -49.10mA -83.72mA -2.50V -61.54mA -47.88mA -80.82mA -2.00V -56.69mA -44.35mA -74.09mA -1.50V -48.49mA -38.12mA -63.07mA -1.00V -36.55mA -28.88mA -47.32mA -0.50V -20.52mA -16.31mA -26.43mA 0.00V -106.55pA -4.99nA -99.23pA 100.00mV 4.53mA 3.63mA 5.79mA 200.00mV 8.80mA 7.03mA 11.29mA 300.00mV 12.89mA 10.27mA 16.56mA 400.00mV 16.80mA 13.36mA 21.61mA ... data omitted ... 4.60V 65.24mA 50.76mA 85.74mA 4.70V 65.33mA 50.85mA 85.81mA 4.80V 65.41mA 50.94mA 85.88mA 4.90V 65.48mA 51.02mA 85.94mA 5.00V 65.55mA 51.11mA 85.99mA 10.00V 69.54mA 55.38mA 89.29mA

Note that the voltages in the pullup and Power_clamp tables are Vcc relative and are derived from the equation:

Vtable = Vcc - Voutput

[Pullup]* Element 3 contains the ground-clamp and power-clamp information. Diode data, when present, appear in this table. These keywords can be omitted.| Voltage I(typ) I(min) I(max) -5.00V 68.15mA 52.44mA 90.50mA -4.50V 66.52mA 51.20mA 88.31mA -4.00V 64.48mA 49.64mA 85.57mA -3.50V 62.05mA 47.79mA 82.33mA -3.00V 59.14mA 45.64mA 78.18mA -2.50V 54.38mA 42.25mA 71.46mA -2.00V 47.43mA 37.07mA 62.02mA -1.50V 38.38mA 30.13mA 49.97mA -1.00V 27.32mA 21.54mA 35.44mA -0.50V 14.45mA 11.44mA 18.67mA 0.00V 94.71pA 4.44nA 88.21pA 100.00mV -3.03mA -2.41mA -3.89mA 200.00mV -5.97mA -4.74mA -7.69mA 300.00mV -8.85mA -7.02mA -11.42mA 400.00mV -11.68mA -9.25mA -15.08mA ... data omitted ... 4.60V -66.88mA -51.47mA -88.79mA 4.70V -67.22mA -51.73mA -89.25mA 4.80V -67.55mA -51.98mA -89.69mA 4.90V -67.86mA -52.21mA -90.11mA 5.00V -68.15mA -52.44mA -90.50mA 10.00V -83.59mA -67.88mA -105.95mA

[GND_clamp]The clamp diode characteristics are meant to be modeled in parallel with the driver information in elements 1 and 2 (pull-down and pull-up), ensuring the diode characteristics are present even when the output buffer is in a high-impedance state (off). The currents listed in the table can be large and are provided only to enable simulators to construct the proper diode curve.| Voltage I(typ) I(min) I(max) -5.00V -2.92A NA NA -1.10V -155.00mA NA NA -1.00V -84.00mA NA NA -900.00mV -46.00mA NA NA -800.00mV -26.10mA NA NA -700.00mV -9.50mA NA NA -600.00mV -3.50mA NA NA -500.00mV -1.11mA NA NA -400.00mV -300.00uA NA NA -300.00mV -155.00uA NA NA -200.00mV -90.00uA NA NA -100.00mV -29.00uA NA NA 0.00V 0.00pA NA NA 5.00V 0.00pA NA NA |

[POWER_clamp]

| Voltage I(typ) I(min) I(max) -5.00V 1.44A NA NA -1.10V 70.70mA NA NA -1.00V 35.60mA NA NA -900.00mV 23.50mA NA NA -800.00mV 12.20mA NA NA -700.00mV 4.55mA NA NA -600.00mV 1.05mA NA NA -500.00mV 415.00uA NA NA -400.00mV 201.00uA NA NA -300.00mV 95.00uA NA NA -200.00mV 40.00uA NA NA -100.00mV 15.00uA NA NA -10.00mV 0.00pA NA NA 0.00V 0.00pA NA NA

* Element 4 contains the ramp time for the pull-up and pull-down structures, which ensures the correct AC operation of the model.

[Ramp]The "min" column represents the longest rise/fall times and the "max" column represents the shortest times. These values often appear very small because they are intrinsic values for the transistors with all packaging and external loads removed. The packaging characteristics are added outside the transistor model (see element #5).| typ min max

dV/dt_r 1.58/309p 1.34/435p 1.86/206p dV/dt_f 1.74/428p 1.48/696p 2.04/234p

* Element 5 contains the component and packaging characteristics, including the inherent capacitance of the silicon portion of the model (the die, not the package). The package is modeled by the parameters R-L-C_pkg, schematically organized as shown in Figure 1. The table supplies the range (minimum to maximum) for each parameter.

[Package]With the IBIS data, interconnect engineers can model the device characteristics for both fast and slow corners. The slow model can be used to determine flight times. The fast model can be used to investigate overshoot, undershoot, and crosstalk. A slow model can be created by combining the minimum currents with the maximum ramp time and the maximum package characteristics. A fast model can be created with the largest currents, the fastest ramp, and the minimum package information.| typ min max

R_pkg 193.0m 125.0m 262.0m L_pkg 8.95nH 6.11nH 11.80nH C_pkg 1.60pF 1.30pF 1.90pF

The minimum and maximum data include both temperature and process variations. Voltage variation is normally adjustable within simulation tools, or you can approximate such variations by shifting the I/V data by the desired voltage tolerance.

Input models do not include elements 1, 2, and 4, since no outputs are present. Consequently, the information for inputs normally includes I/V curves for the diodes only, and no ramp times.

**Figure 3: Typical Output Gate**

**Figure 4: SPICE vs IBIS waveform comparison.**

|**************************************************************************** | [IBIS Ver] 1.1 [File name] 82433lx.ibs [File Rev] 2.11 [Date] 5/13/94 [Source] File originated at Intel Corporation. [Notes] The following information corresponds to the MERCURY LBX chip. AXAM1058 [Disclaimer] This information is for modeling purposes only, and is not guaranteed. | |**************************************************************************** | [Component] 82433LX [Manufacturer] Intel [Package] | typ min max R_pkg 193.0m 125.0m 262.0m L_pkg 8.95nH 6.11nH 11.80nH C_pkg 1.60pF 1.30pF 1.90pF | |**************************************************************************** | [Pin] signal_name model_name | 1 VDD POWER 2 VSS GND 3 NC NC | Phase Lock Loop 4 NC NC | Filter Circuit 5 NC NC | | | 6 NC NC | | | 7 NC NC | V V 8 HCLK BX777700 9 TEST BX777700 10 D6 BX08081A 11 D2 BX08081A ... data omitted ... 157 D15 BX08081A 158 D13 BX08081A 159 D9 BX08081A 160 VDD POWER | |**************************************************************************** | BX121222 MODEL |**************************************************************************** | [Model] BX121222 Model_type I/O Polarity Non-Inverting Enable Active-Low | Signals A[0-15] | Vinl = 0.8V Vinh = 2.0V | typ min max C_comp 4.90pF 2.70pF 7.10pF | | typ min max [Voltage range] 5.0V 4.75V 5.25V | [Pulldown] | Voltage I(typ) I(min) I(max) -5.00V -65.55mA -51.11mA -85.99mA -4.50V -65.16mA -50.67mA -85.66mA -4.00V -64.67mA -50.20mA -85.18mA ... data omitted ... 4.90V 65.48mA 51.02mA 85.94mA 5.00V 65.55mA 51.11mA 85.99mA 10.00V 69.54mA 55.38mA 89.29mA | [GND_clamp] | Voltage I(typ) I(min) I(max) -5.00V -2.92A NA NA -1.10V -155.00mA NA NA -1.00V -84.00mA NA NA ... data omitted ... -200.00mV -90.00uA NA NA -100.00mV -29.00uA NA NA 0.00V 0.00pA NA NA 5.00V 0.00pA NA NA | [Pullup] | Voltage I(typ) I(min) I(max) -5.00V 68.15mA 52.44mA 90.50mA -4.50V 66.52mA 51.20mA 88.31mA -4.00V 64.48mA 49.64mA 85.57mA ... data omitted ... 4.90V -67.86mA -52.21mA -90.11mA 5.00V -68.15mA -52.44mA -90.50mA 10.00V -83.59mA -67.88mA -105.95mA | [POWER_clamp]| Voltage I(typ) I(min) I(max) -5.00V 1.44A NA NA -1.10V 70.70mA NA NA -1.00V 35.60mA NA NA ... data omitted ... -100.00mV 15.00uA NA NA -10.00mV 0.00pA NA NA 0.00V 0.00pA NA NA | [Ramp] | typ min max dV/dt_r 1.58/309p 1.34/435p 1.86/206p dV/dt_f 1.74/428p 1.48/696p 2.04/234p |

|**************************************************************************** | BX061202 MODEL |**************************************************************************** | [Model] BX061202 Model_type I/O Polarity Non-Inverting Enable Active-Low | Signals AD[0-15] | Vinl = 0.8V Vinh = 2.0V | typ min max C_comp 4.90pF 2.70pF 7.10pF | | typ min max [Voltage range] 5.0V 4.75V 5.25V | [Pulldown] | Voltage I(typ) I(min) I(max) -5.00V -147.50mA -114.98mA -193.48mA -4.50V -146.60mA -114.02mA -192.73mA -4.00V -145.50mA -112.95mA -191.64mA ... data omitted ... 4.90V 147.33mA 114.80mA 193.36mA 5.00V 147.50mA 114.98mA 193.48mA 10.00V 156.47mA 124.61mA 200.90mA | [GND_clamp] | Voltage I(typ) I(min) I(max) -5.00V -2.92A NA NA -1.10V -155.00mA NA NA -1.00V -84.00mA NA NA ... data omitted ... -100.00mV -29.00uA NA NA 0.00V 0.00pA NA NA 5.00V 0.00pA NA NA | [Pullup] | Voltage I(typ) I(min) I(max) -5.00V 90.87mA 69.92mA 120.67mA -4.50V 88.69mA 68.26mA 117.74mA -4.00V 85.97mA 66.19mA 114.10mA ... data omitted ... 4.90V -90.48mA -69.62mA -120.14mA 5.00V -90.87mA -69.92mA -120.67mA 10.00V -111.46mA -90.51mA -141.26mA | [POWER_clamp] | Voltage I(typ) I(min) I(max) -5.00V 1.44A NA NA -1.10V 70.70mA NA NA -1.00V 35.60mA NA NA ... data omitted ... -100.00mV 15.00uA NA NA -10.00mV 0.00pA NA NA 0.00V 0.00pA NA NA | [Ramp] | typ min max dV/dt_r 1.85/852p 1.60/1.20n 2.12/572p dV/dt_f 2.42/1.01n 2.19/1.33n 2.65/624p | |**************************************************************************** | BX08081A MODEL |**************************************************************************** | [Model] BX08081A Model_type I/O Polarity Non-Inverting Enable Active-Low | The model is a BX080812 with a pull-up resistor.

| Signals D[0-31], HP[0-3] | ... data omitted ... | |**************************************************************************** | BX04040A MODEL |**************************************************************************** | [Model] BX04040A Model_type I/O Polarity Non-Inverting Enable Active-Low | The model is a BX040402 with a pull-up resistor. | Signals MD[0-31], MP[0-3] | ... data omitted ... | |**************************************************************************** | BX060612 MODEL |**************************************************************************** | [Model] BX060612 Model_type I/O Enable Active-Low Polarity Non-Inverting | Signals PPOUT, EOL | ... data omitted ... | |**************************************************************************** | BX777700 MODEL |**************************************************************************** | [Model] BX777700 Model_type Input | Signals HCLK, TRDY, RESET, PCLK | ... data omitted ... | |**************************************************************************** | BX77770V MODEL |**************************************************************************** | [Model] BX77770V Model_type Input | Signals HIG[0-4], MIG[0-2], MDLE | DRVPCI, PIG[0-3] | ... data omitted ... | [End]

An ARPA funded project to develop a SPICE-to-IBIS translator was done at North Carolina State University by Steve Lipa under the direction of Michael Steer and Paul Franzon with collaboration from Interconnectix, Inc. The program works with existing Berkeley 2 and 3, MicroSim Pspice, and Meta- Software HSPICE compatible buffer models. Through actual execution under a suite of test conditions, an IBIS formatted model is produced using actual simulation results. This program will be made available in the public domain so semiconductor vendors and end users can generate IBIS models from available SPICE models. The source code for this program will also be available so vendors can configure it as appropriate to work with proprietary versions of SPICE, proprietary process-level models, and with internal knowledge of the validation and accuracy of the internal models. Through such a proces, accurate and representative IBIS models can be rapidly produced.

The IBIS_CHK golden parser program is a very useful model-verification tool. It checks IBIS files for compliance with the IBIS specification and formatting rules. Its coverage is comprehensive to the point that the parser serves as the defacto operational “specification” of IBIS. It checks for correct syntax and inclusion of required keywords, and detects inappropriate use of certain constructs.

IBIS information is available on-line via Internet email (send your email address to ibis-info@vhdl.org, the domain is 198.31.14.3), anonymous ftp, and a number of BBS including CompuServe. Use either anonymous login or anonymous ftp (with no password) on the VHDL International BBS, (414) 335-0110. Documentation, as well as publicly available IBIS files, reside in vhdl.org in the pub/ibis directory. To get on the IBIS Open Forum email list, send a request to ibis-request@vhdl.org.