***************************************************************************** ***************************************************************************** BIRD ID#: 144.3 ISSUE TITLE: Add Touchstone to [External Model] and [External Circuit] as a Supported Language REQUESTER: Taranjit Kukal, Feras Al-Hawari, Ambrish Varma, Terry Jernberg, Cadence Design Systems, Inc.; Kent Dramstad, Adge Hawes, IBM Microelectronics DATE SUBMITTED: September 19, 2011 DATE REVISED: November 10, 2011; February 10, 2012; March 5, 2011 DATE ACCEPTED BY IBIS OPEN FORUM: Rejected April 26, 2013 ***************************************************************************** ***************************************************************************** Lines beginning with * or |* indicate changes in BIRD144 Lines beginning with ** or |** indicate changes in BIRD144.1 Lines beginning with *** or |*** indicate changes in BIRD144.2 Lines beginning with **** or |**** indicate changes in BIRD144.3 STATEMENT OF THE ISSUE: ** S-parameter data can be used, for example, to describe transfer characteristics of I/O buffer amplifiers, On DIE Terminations (ODT), and On DIE RDL ** parasitics. Mostly, the S-parameter data is saved according to the ** Touchstone file format. Therefore, adding Touchstone to the list of languages that are supported by the [External Model] and [External Circuit] ** sections would enable the direct usage of Touchstone S-parameter files in IBIS without the need to wrap and instantiate such models in a SPICE like subcircuit. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: ** The new "Touchstone" option shall be added to the list of options supported by the Language subparameter under the [External Model] and [External Circuit] ** sections. The usage rules of the Touchstone language are very similar to those of the SPICE like language options. Replace all occurrences of: SPICE, Verilog-A(MS), VHDL-A(MS) SPICE, Verilog-A(MS) or VHDL-A(MS) SPICE, Verilog-A(MS) and VHDL-A(MS) with: ** SPICE, Touchstone, Verilog-A(MS), VHDL-A(MS) ** SPICE, Touchstone, Verilog-A(MS) or VHDL-A(MS) ** SPICE, Touchstone, Verilog-A(MS) and VHDL-A(MS) Replace all occurrences of: SPICE, VHDL-A(MS), Verilog-A(MS) SPICE, VHDL-A(MS) or Verilog-A(MS) SPICE, VHDL-A(MS) and Verilog-A(MS) with: ** SPICE, Touchstone, VHDL-A(MS), Verilog-A(MS) ** SPICE, Touchstone, VHDL-A(MS) or Verilog-A(MS) ** SPICE, Touchstone, VHDL-A(MS) and Verilog-A(MS) ** On page 99 in the IBIS 5.0 specification, insert after the following lines: ** | "SPICE" refers to SPICE 3, Version 3F5 developed by the University of ** | California at Berkeley, California. Many vendor-specific EDA tools are ** | compatible with most or all of this version. ** these lines: |** "Touchstone" refers to the Touchstone file format version 1.0, version 2.0 |** (ratified April 24, 2009 by the IBIS Open Forum), or later. It is the de facto |** industry-standard ASCII text file format used for documenting the n-port |** network parameter data and noise data of linear active devices, passive |** filters, passive devices, or interconnect networks. It allows representing |** the the n-port network using S-parameter, Y-parameter and Z-parameter data. |* ------------------------------------------------------ Add D_drive_pos and D_drive_neg to the reserved ports ------------------------------------------------------ ** On page 101 in the IBIS 5.0 specification, insert after the following lines: |** 12 A_pos Non-inverting port for series or series switch models |** 13 A_neg Inverting port for series or series switch models |** 14 A_signal_pos Non-inverting port of a differential model |** 15 A_signal_neg Inverting port of a differential model these lines: |* 16 D_drive_pos Non-inverting digital input port of a differential model |* 17 D_drive_neg Inverting digital input port of a differential model ** On page 105 of the IBIS 5.0 specification, replace the following line: | Sub-Params: Language, Corner, Parameters, Ports, D_to_A, A_to_D ** with: |*** Sub-Params: Language, Corner, Parameters, Ports, Port_termination, |*** D_to_A, A_to_D ** On page 107 of the IBIS 5.0 specification, replace the following lines: | The circuit_name entry provides the name of the circuit to be | simulated within the referenced file. For SPICE files, this | is normally a ".subckt" name. For VHDL-AMS files, this is | normally an "entity(architecture)" name pair. For Verilog-AMS | files, this is normally a "module" name. with: | The circuit_name entry provides the name of the circuit to be | simulated within the referenced file. For SPICE files, this | is normally a ".subckt" name. For VHDL-AMS files, this is | normally an "entity(architecture)" name pair. For Verilog-AMS |** files, this is normally a "module" name. For Touchstone files, |* the circuit_name is not applicable and should be "NA". *** On page 108 of the IBIS 5.0 specification, insert after the following lines: | [Pullup Reference], [Pulldown Reference], and/or [Voltage | Range] keywords, as in the case of [Model]. *** these lines: |*** Port_termination: |*** |**** The Port_termination subparameter may be used to inform the |**** simulation tool how: 1) to terminate a floating (unused) |**** reserved [External Model] port, or 2) to add a termination |**** resistor between a reserved [External Model] port and one |**** of the Touchstone model nodes. |*** |**** The Port_termination subparameter is followed by four |*** arguments: |**** reserved_port ts_port resistor_value voltage_value |*** |*** The reserved port entry holds the name of the reserved port to be |*** terminated e.g., A_puref, A_pcref, A_pdref, A_gcref, or D_enable. |**** The simulation tool should connect the reserved_port to one of the |**** nodes of the termination resistor. |**** |**** The ts_port holds the name of the Touchstone port to be connected |**** by the simulation tool to the other node of the termination |**** resistor. Note that when a voltage_value is specified, then the |**** the ts_port must be NA. |**** |**** The resistor_value holds the resistance value (in ohms) of the |**** termination resistor that the simulation tool should use. |**** |**** The voltage_value holds the voltage value (in volts) of the independent |**** DC reference voltage source to be connected by the simulation tool |**** to the other node of the termination resistor when the ts_port is NA. |**** Note that the other node of the DC voltage source should be connected |**** by the simulation tool to ideal ground. |*** ** On page 125 of the IBIS 5.0 specification, replace the following lines: | The circuit_name entry provides the name of the circuit to be | simulated within the referenced file. For SPICE files, this | is normally a ".subckt" name. For VHDL-AMS files, this is | normally an "entity(architecture)" name pair. For Verilog-AMS | files, this is normally a "module" name. with: | The circuit_name entry provides the name of the circuit to be | simulated within the referenced file. For SPICE files, this | is normally a ".subckt" name. For VHDL-AMS files, this is | normally an "entity(architecture)" name pair. For Verilog-AMS |** files, this is normally a "module" name. For Touchstone files, |** the circuit_name is not applicable and should be "NA". --------------------------------------------- ** EXAMPLES for [External Model] using Touchstone --------------------------------------------- ** Add these lines after the SPICE example in page 118 of the IBIS 5.0 specification: |--------------------------------------------------------------------- |** Example [External Model] using Touchstone: |--------------------------------------------------------------------- | |**** +-------------------------------+ |**** | | |**** | 1e6 ohms | |**** A_pcref---|--/\/\/\--o Vref=0.0V | |**** | | |**** | 1e6 ohms | |**** A_puref---|--/\/\/\--o Vref=0.0V | |**** | | |**** | +------------+ | |**** | | | | |**** my_drive-->|-------------|1 TS 2|----|-->A_signal |**** | | | | |**** | +------------+ | |**** | | |**** | 1e6 ohms | |**** A_pdref---|--/\/\/\--o Vref=0.0V | |**** | | |**** | 1e6 ohms | |**** A_gcref---|--/\/\/\--o Vref=0.0V | |**** | | |**** +-------------------------------+ | | [Model] ExLinearBufferTouchstone Model_type Output | | Other model subparameters are optional | | typ min max [Voltage Range] 3.3 3.0 3.6 | [Ramp] dV/dt_r 1.57/0.36n 1.44/0.57n 1.73/0.28n dV/dt_f 1.57/0.35n 1.46/0.44n 1.68/0.28n | [External Model] ** Language Touchstone | | Corner corner_name file_name circuit_name Corner Typ buffer_typ.s2p NA Corner Min buffer_min.s2p NA Corner Max buffer_max.s2p NA | |** Ports List of port names (in same order as in Touchstone) ** Ports my_drive A_signal | my_drive should be connected to port 1 of Touchstone ** | A_signal should be connected to port 2 of Touchstone |*** |**** Port_termination reserved_port ts_port resistor_value voltage_value **** Port_termination A_puref NA 1e6 0.0 **** Port_termination A_pcref NA 1e6 0.0 **** Port_termination A_pdref NA 1e6 0.0 **** Port_termination A_gcref NA 1e6 0.0 | | D_to_A d_port port1 port2 vlow vhigh trise tfall corner_name D_to_A D_drive my_drive A_pdref 0.0 3.3 0.5n 0.3n Typ | [End External Model] | ** Add these lines after the SPICE example in page 122 of the IBIS 5.0 specification: |------------------------------------------------------------------- |** Example of True Differential [External Model] using Touchstone: |------------------------------------------------------------------- | |**** +-------------------------------+ |**** | | |**** | 1e6 ohms | |**** A_pcref---|--/\/\/\--o Vref=0.0V | |**** | | |**** | 1e6 ohms | |**** A_puref---|--/\/\/\--o Vref=0.0V | |**** | | |**** | +------------+ | |**** | 50 ohms | | | |**** my_drive_pos-->|--/\/\/\--o--|1 2|----|-->A_signal_pos |**** | | | | |**** | | TS | | |**** | 50 ohms | | | |**** my_drive_neg-->|--/\/\/\--o--|3 4|----|-->A_signal_neg |**** | | | | |**** | +------------+ | |**** | | |**** | 1e6 ohms | |**** A_pdref---|--/\/\/\--o Vref=0.0V | |**** | | |**** | 1e6 ohms | |**** A_gcref---|--/\/\/\--o Vref=0.0V | |**** | | |**** +-------------------------------+ | [Model] Ext_Linear_Diff_Output_Buff_Touchstone Model_type Output_diff Rref_diff = 100 | | Other model subparameters are optional | | typ min max [Voltage Range] 3.3 3.0 3.6 | [Ramp] dV/dt_r 1.57/0.36n 1.44/0.57n 1.73/0.28n dV/dt_f 1.57/0.35n 1.46/0.44n 1.68/0.28n | [External Model] ** Language Touchstone | | Corner corner_name file_name circuit_name Corner Typ diffout_typ.s4p NA Corner Min diffout_min.s4p NA Corner Max diffout_max.s4p NA | |** Ports List of port names (in same order as in Touchstone) | | Based on the Ports order below: |** my_drive_pos should be connected to port 1 of Touchstone |** A_signal_pos should be connected to port 2 of Touchstone |** my_drive_neg should be connected to port 3 of Touchstone |** A_signal_neg should be connected to port 4 of Touchstone | Ports my_drive_pos A_signal_pos my_drive_neg A_signal_neg |*** |**** Port_termination reserved_port ts_port resistor_value voltage_value **** Port_termination A_puref NA 1e6 0.0 **** Port_termination A_pcref NA 1e6 0.0 **** Port_termination A_pdref NA 1e6 0.0 **** Port_termination A_gcref NA 1e6 0.0 **** Port_termination my_drive_pos 1 50 NA **** Port_termination my_drive_neg 3 50 NA | | D_to_A d_port port1 port2 vlow vhigh trise tfall corner_name D_to_A D_drive_pos my_drive_pos A_pdref 0.0 3.3 0.5n 0.3n Typ D_to_A D_drive_pos my_drive_pos A_pdref 0.0 3.0 0.6n 0.3n Min D_to_A D_drive_pos my_drive_pos A_pdref 0.0 3.6 0.4n 0.3n Max D_to_A D_drive_neg my_drive_neg A_pdref 0.0 3.3 0.5n 0.3n Typ D_to_A D_drive_neg my_drive_neg A_pdref 0.0 3.0 0.6n 0.3n Min D_to_A D_drive_neg my_drive_neg A_pdref 0.0 3.6 0.4n 0.3n Max | [End External Model] ----------------------------------------------- ** EXAMPLES on [External Circuit] using Touchstone ----------------------------------------------- ** Add these lines after the SPICE example in page 129 of the IBIS 5.0 specification: |--------------------------------------------- |** Example [External Circuit] using Touchstone: |--------------------------------------------- | ** [External Circuit] LINEAR-OUTBUFF-Touchstone ** Language Touchstone | | Corner corner_name file_name circuit_name Corner Typ buffer_typ.s2p NA Corner Min buffer_min.s2p NA Corner Max buffer_max.s2p NA | |** Ports List of port names (in same order as in Touchstone) ** Ports my_in A_signal | my_in should be connected to port 1 of Touchstone ** | A_signal should be connected to port 2 of Touchstone | | D_to_A d_port port1 port2 vlow vhigh trise tfall corner_name D_to_A D_drive my_in A_pdref 0.0 3.3 0.5n 0.3n Typ D_to_A D_drive my_in A_pdref 0.0 3.0 0.6n 0.3n Min D_to_A D_drive my_in A_pdref 0.0 3.6 0.4n 0.3n Max | [End External Circuit] | ** Add these lines after the SPICE example in page 131 of the IBIS 5.0 specification: |--------------------------------------------- |** Example [External Circuit] using Touchstone: |--------------------------------------------- | ** [External Circuit] BUS_Touchstone ** Language Touchstone | | Corner corner_name file_name circuit_name Corner Typ bus_typ.s14p NA Corner Min bus_min.s14p NA Corner Max bus_max.s14p NA | |** Ports are in same order as defined in Touchstone | | Based on the Ports order below: |** vcc should be connected to port 1 of Touchstone |** gnd should be connected to port 2 of Touchstone |** io1 should be connected to port 3 of Touchstone |** io2 should be connected to port 4 of Touchstone |** int_ioa should be connected to port 5 of Touchstone |** vcca1 should be connected to port 6 of Touchstone |** vcca2 should be connected to port 7 of Touchstone |** vssa1 should be connected to port 8 of Touchstone |** vssa2 should be connected to port 9 of Touchstone |** int_iob should be connected to port 10 of Touchstone |** vccb1 should be connected to port 11 of Touchstone |** vccb2 should be connected to port 12 of Touchstone |** vssb1 should be connected to port 13 of Touchstone |** vssb2 should be connected to port 14 of Touchstone | Ports vcc gnd io1 io2 Ports int_ioa vcca1 vcca2 vssa1 vssa2 Ports int_iob vccb1 vccb2 vssb1 vssb2 | | No A_to_D or D_to_A required, as no digital ports are used | [End External Circuit] ***************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION The parameters defined in this BIRD came from commercial S-parameter-AMI model development efforts and SPICE-IO-AMI modeling efforts where new functionality was needed to meet customer expectations for model functionality, accuracy and performance. The parameters in this BIRD were defined by Cadence and its semiconductor partners. These parameters are being contributed to IBIS to ensure SPICE-AMI model accuracy and portability. ** The D_drive_pos and D_drive_neg ports are needed to allow the model maker to make ** differential buffer models with two ports for the stimulus input, one using ** a non-inverted, and the other using an inverted stimulus signal. Note that, ** BIRD 129 also addresses the previous issue in a slightly different manner. ** Our proposed approach can also make use of the polarity argument proposed ** in BIRD 129 to make it possible to put the converter into an inverted mode of ** operation. Preferably, our syntax as well as the syntax in BIRD 129 may be ** consolidated to provide a more robust solution. We will leave it to the IBIS ** steering committee to decide on this matter. ***************************************************************************** ANY OTHER BACKGROUND INFORMATION: As Touchstone is supported by IBIS-ISS and IBIS-ISS connections are supported by BIRD160.1, this BIRD was rejected by the IBIS Open Forum at its April 26, 2013 teleconference. *****************************************************************************