****************************************************************************** ****************************************************************************** BIRD ID#: 75.8 ISSUE TITLE: Multi-Lingual Model Support REQUESTER: Bob Ross and Chris Reid, Mentor Graphics, Arpad Muranyi and Michael Mirmak, Intel DATE SUBMITTED: 3/29/02, 5/3/02, 7/15/02, 8/14/02, 9/11/02, 9/27/02, 10/18/02, 12/20/02, 12/23/02 DATE ACCEPTED BY IBIS OPEN FORUM: 1/10/03 ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: A rapid solution is needed for modeling on-die interconnect circuitry and more complex buffer structures than what IBIS currently supports. The IBIS specification already has too many keywords to support additional expansion on an incremental basis as new technologies are introduced. The process of developing an entirely new specification (IBIS-X) to address these issues is turning out to be more time-consuming than anticipated. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: Multi-lingual model support within IBIS can leverage publicly accepted and standardized language implementations such as SPICE, VHDL-AMS, Verilog-AMS, etc. to support extended buffer behavior and extended interconnect descriptions. This proposal still uses much of IBIS directly for pinout, package, specification, and other content and proposes linking to external code for an additional method to model and report electrical performance. A new Section 6b describes these extensions. In addition, Section 3, (2) is modified with a new reserved word CIRCUITCALL: | 2) The following words are reserved words and must not be used for | any other purposes in the document: | POWER - reserved model name, used with power supply pins, | GND - reserved model name, used with ground pins, | NC - reserved model name, used with no-connect pins, | NA - used where data not available, | CIRCUITCALL - used for circuit call references in Section 6b. | The Section 6b addition is below: |============================================================================= |============================================================================= | | Section 6b | | M U L T I - L I N G U A L M O D E L E X T E N S I O N S | |============================================================================= |============================================================================= | | INTRODUCTION: | | The SPICE, VHDL-AMS and Verilog-AMS languages are supported by IBIS. This | chapter describes how models written in these languages can be referenced | and used by IBIS files. | | The language extensions use the following keywords within the IBIS framework: | | [External Circuit] - References enhanced descriptions of structures | [End External Circuit] on the die, including digital and/or analog, | active and/or passive circuits | | [External Model] - Same as [External Circuit], except limited to | [End External Model] the connection format and usage of the [Model] | keyword, with one additional feature added: | support for true differential buffers | | [Node Declarations] - Lists on-die connection points related to | [End Node Declarations] the [Circuit Call] keyword | | [Circuit Call] - Instantiates [External Circuit]s and connects | [End Circuit Call] them to each other and/or die pads | | The placement of these keywords within the hierarchy of IBIS is shown in the | following diagram: | | | |-- [Component] | | | ... | | |-- [Node Declarations] | | |-- [End Node Declarations] | | | ... | | | ... | | |-- [Circuit Call] | | |-- [End Circuit Call] | | | ... | | ... | |-- [Model] | | | ... | | |-- [External Model] | | |-- [End External Model] | | | ... | | ... | |-- [External Circuit] | |-- [End External Circuit] | | ... | | Figure 1 | | | LANGUAGES SUPPORTED: | | IBIS files can reference other files which are written using the SPICE, | VHDL-AMS, or Verilog-AMS languages. In this document, these languages | are defined as follows: | | "SPICE" refers to SPICE 3, Version 3F5 developed by the University of | California at Berkeley, California. Many vendor-specific EDA tools are | compatible with most or all of this version. | | "VHDL-AMS" refers to "IEEE Standard VHDL Analog and Mixed-Signal | Extensions", approved March 18, 1999 by the IEEE-SA Standards Board and | designated IEEE Std. 1076.1-1999. | | "Verilog-AMS" refers to the Analog and Mixed-Signal Extensions to | Verilog-HDL as documented in the Verilog-AMS Language Reference, Version | 2.0. This document is maintained by Accellera (formerly Open Verilog | International), an independent organization. Verilog-AMS is a superset | that includes Verilog-A and the Verilog Hardware Description Language | IEEE 1364-2001. | | In addition the "IEEE Standard Multivalue Logic System for VHDL Model | Interoperability (Std_logic_1164)" designated IEEE Std. 1164-1993 is | required to promote common digital data types. | | Note that, for the purposes of this section, keywords, subparameters and | other data used without reference to the external languages just described | are referred to collectively as "native" IBIS. | | OVERVIEW: | | The four keyword pairs discussed in this chapter can be separated into | two groups based on their functionalities. The [External Model], [End | External Model], [External Circuit] and [End External Circuit] keywords | are used as pointers to the models described by one of the external | languages. The [Node Declaration], [End Node Declaration], [Circuit Call] | and [End Circuit Call] keywords are used to describe how [External | Circuit]s are connected to each other and/or to the die pads. | | The [External Model] and [External Circuit] keywords are very similar in | that they both support the same external languages, and they can both be | used to describe passive and/or active circuitry. The key difference | between the two keywords is that [External Model] can only be placed under | the [Model] keyword, while [External Circuit] can only be placed outside | the [Model] keyword. This is illustrated in Figure 1 above. | | The intent behind [External Model] is to provide an upgrade path from | native IBIS [Model]s to the external languages (one exception to this is the | support for true differential buffers). Thus, the [External Model] keyword | can be used to replace the usual I-V and V-T tables, C_comp, C_comp_pullup, | C_comp_pulldown, C_comp_power_clamp, C_comp_gnd_clamp subparameters, | [Ramp], [Driver Schedule], [Submodel] keywords, etc... of a [Model] | by any modeling technique that the external languages allow. For [External | Model]s, the connectivity, test load and specification parameters (such as | Vinh and Vinl) are preserved from the [Model] keyword and the simulator is | expected to carry out the same type of connections and measurements as is | usually done with the [Model] keyword. The only difference is that the | model itself is described by an external language. | | In the case of the [External Circuit], however, one can model a circuit | having any number of ports (see definitions below). For example, the | ports may include impedance or buffer strength selection controls in | addition to the usual signal and supply connections. The connectivity of | an [External Circuit] is defined by the [Node Declaration] and [Circuit | Call] keywords. Currently, the test loads and measurement parameters for | an [External Circuit] can only be defined inside the model description | itself. The results of measurements can be reported to the user or tool | via other means. | | The [Circuit Call] keyword acts similarly to subcircuit calls in SPICE, | instantiating the various [External Circuit]s and connecting them | together. Please note that models described by the [External Model] | keyword are connected according to the rules and assumptions of the | [Model] keyword. [Circuit Call] is not necessary for these cases and must | not be used. | | | DEFINITIONS: | | For the purposes of this document, several general terms are defined below. | | circuit - any arbitrary collection of active or | passive electrical elements treated as a unit | | node - any electrical connection point; | also called die node (may be digital or | analog; may be a connection internal to a | circuit or between circuits) | | pad - a special case of a node. A pad connects | a buffer or other circuitry to a package; | also called die pad. | | port - access point in an [External Model] or | [External Circuit] definition for digital or | analog signals | | pseudo-differential circuits - combination of two single-ended circuits which | drive and/or receive complementary signals, | but where no internal current relationship | exists between them | | true differential circuits - circuits where a current relationship exists | between two output or inputs which drive or | receive complementary signals | | | | GENERAL ASSUMPTIONS: | | | Ports under [Model]s: | | The use of ports under native IBIS must be understood before the multi- | lingual extensions can be correctly applied. The [Model] keyword assumes, | but does not explicitly require naming ports on circuits. These ports are | automatically connected by IBIS-compliant tools without action by the user. | For example, the [Voltage Reference] keyword implies the existence of power | supply rails which are connected to the power supply ports of the circuit | described by the [Model] keyword. | | For multi-lingual modeling, ports must be explicitly named in the | [External Model] or [External Circuit]; the ports are no longer assumed by | EDA tools. To preserve compatibility with the assumptions of [Model], a | list of pre-defined port names has been created where the ports are | reserved with fixed functionality. These reserved ports are defined in the | table below. | | Port Name Description | ========= ========================== | 1 D_drive Digital input to a model unit | 2 D_enable Digital enable for a model unit | 3 D_receive Digital receive port of a model unit, based on data on | A_signal (and/or A_signal_pos and A_signal_neg) | 4 A_puref Voltage reference port for pullup structure | 5 A_pcref Voltage reference port for power clamp structure | 6 A_pdref Voltage reference port for pulldown structure | 7 A_gcref Voltage reference port for ground clamp structure | 8 A_signal I/O signal port for a model unit | 9 A_extref External reference voltage port | 10 D_switch Digital input for control of a series switch model | 11 A_gnd Global reference voltage port | 12 A_pos Non-inverting port for series or series switch models | 13 A_neg Inverting port for series or series switch models | 14 A_signal_pos Non-inverting port of a differential model | 15 A_signal_neg Inverting port of a differential model | | The first letter of the port name designates it as either digital ("D") or | analog ("A"). Reserved ports 1 through 13 listed above are assumed or | implied under the native IBIS [Model] keyword. Again, for multi-lingual | models, these ports must be explicitly assigned by the user in the model | if their functions are to be used. A_gnd is a universal reference node, | similar to SPICE ideal node "0." Ports 14 and 15 are only available | under [External Model] for support of true differential buffers. | | Under the [Model] description, power and ground reference ports are | created and connected by IBIS-compliant tools as defined by the [Power | Clamp Reference], [GND Clamp Reference], [Pullup Reference], [Pulldown | Reference] and/or [Voltage Range] keywords. The A_signal port is connected | to the die pad, to drive or receive an analog signal. | | | Ports under [External Model]s: | | The [External Model] keyword may only appear under the [Model] keyword and | it may only use the same ports as assumed with the native IBIS [Model] | keyword. However, [External Model] requires that reserved ports be | explicitly declared in the referenced language(s); tools will continue to | assume the connections to these ports. | | For [External Model], reserved analog ports are usually assumed to be die | pads. These ports would be connected to the component pins through [Package | Model]s or [Pin] parasitics. Digital ports under [External Model] would | connect to other internal digital circuitry. | | Drawings of two standard [Model] structures -- an I/O buffer and a Series | Switch -- are shown below, with their associated port names. | | +---------+ | D_enable---| |---A_puref | ||\ |---A_pcref | D_drive----|| >----+-----A_signal | ||/ /| | |---A_gcref | D_receive--| < |--+ |---A_pdref | | \| |---A_gnd | | |---A_extref | +---------+ | | Figure 2 | | | +---------+ | | | | | +----|---A_pos | | ||-+ | | D_switch----| || | | | ||-+ | | | +----|---A_neg | | | | +---------+ | | Figure 3 | | | Ports under [External Circuit]s: | | The [External Circuit] keyword allows the user to define any number of | ports and port functions on a circuit. The [Circuit Call] keyword | instantiates [External Circuit]s and connects their ports to specific die | nodes (this can include pads). In this way, the ports of an [External | Circuit] declaration become specific component die nodes. Note that, if | reserved digital port names are used with an [External Circuit], those ports | will be connected automatically as defined in the port list above (under | [External Circuit], reserved analog port names do not retain particular | meanings). | | The diagram below illustrates the use of [External Circuit]. Buffer A | is an instance of [External Circuit] "X". Similarly, Buffer B is an | instance of [External Circuit] "Z". These instances are created through | [Circuit Call]s. [External Circuit] "Y" defines an on-die interconnect | circuit. Nodes "a" through "e" and nodes "f" through "j" are specific | instances of the ports defined for [External Circuit]s "X" and "Z". These | ports become the internal nodes of the die and must be explicitly declared | with the [Node Declaration] keyword. The "On-die Interconnect" [Circuit | Call] creates an instance of the [External Circuit] "Y" and connects the | instance with the appropriate power, signal and ground die pads. The "A" | and "B" [Circuit Call]s connect the individual ports of each buffer | instance to the "On-die Interconnect" [Circuit Call]. | | Note that the "Analog Buffer Control" signal is connected directly to the | pad for pin 3. This connection is also made through an entry under the | [Circuit Call] keyword. | | -------------------------------------------------+ | Buffers and interconnect instantiated and | | internal nodes connected through [Circuit Call] | Die Pads | | (map to pins through | [External Circuit] X [External Circuit] Y | package) | +---------+ +--------------------+ | | | A |--a--|vcca1 vcc|---*| 10 Vcc | ||\ |--b--|vcca2 | | | || >----+----c--|int_ioa io1|---*| 1 I/O pad A | ||/ /| | |--d--|vssa1 | | | | < |--+ |--e--|vssa2 gnd|---*| 11 GND | | \| | | | | | +---------+ | On-die | | | | Interconnect | | | | | | | [External Circuit] Z| | | | +---------+ | | | | | B |--f--|vccb1 | | | ||\ |--g--|vccb2 | | | || >----+----h--|int_iob io2|---*| 2 I/O pad B | ||/ /| | |--i--|vssb1 | | | | < |--+ |--j--|vssb2 | | | | \| | | | | | +---+-----+ +--------------------+ | | | | | | Analog Buffer Control | | +------------------------------------*| 3 Control Resistor | | or Voltage | -------------------------------------------------+ | | Figure 4 | | The [Model], [External Model] and [External Circuit] keywords (with | [Circuit Call]s and [Node Declarations] as appropriate) may be combined | together in the same IBIS file or even within the same [Component] | description. | | | SPICE versus VHDL-AMS and VERILOG-AMS | | The intent of native IBIS is to model the circuit block between the region | where analog signals are of interest, and the digital logic domain internal | to the component. (for the purposes of this discussion, the IBIS circuit | block is called a "model unit" in the drawings and document text below). | | The multi-lingual modeling extensions maintain and expand this approach, | assuming that both digital signals and/or analog signals can move to | and from the model unit. All VHDL-AMS and Verilog-AMS models, therefore | must have digital ports and analog ports (in certain cases, digital | ports may not be required, as in the case of interconnects; see | [External Circuit] below). Routines to convert signals from one | format to the other are the responsibility of the model author. | | SPICE cannot process digital signals. All SPICE input and output signals | must be in analog format. Consequently, IBIS multi-lingual models using | SPICE require analog-to-digital (A_to_D) and/or digital-to-analog (D_to_A) | converters to be provided by the EDA tool. The converter subparameters are | declared by the user, as part of the [External Model] or [External Circuit] | syntax, with user-defined names for the ports which connect the converters to | the analog ports of the SPICE model. The details behind these | declarations are explained in the keyword definitions below. | | To summarize, Verilog-AMS and VHDL-AMS contain all the capability needed to | ensure that a model unit consists of only digital ports and/or analog ports. | SPICE, however, needs extra data conversion, provided by the EDA tool, to | ensure that any digital signals can be correctly processed. | | | +===================+ | ! "Model Unit" ! | D_receive ---! conversions !--- A_signal | ! provided by !--- A_pcref | D_enable --->! model author !--- A_gcref | ! ! | +===================+ | Model Unit consists only of AMS code | (a_gnd and a_extref are not shown) | | Figure 5: AMS Model Unit, using an I/O buffer as an example | | | +===================================================+ | ! "Model Unit" +-------+! | ! +--------+ | |! | D_receive ---!-<| A_to_D |--< (analog receive ports) --<| |!-- A_puref | ! +--------+ | |! | ! | |!-- A_pdref | ! +--------+ | SPICE |! | D_drive ---!->| D_to_A |--> (analog drive ports) -->| code |!-- A_signal | ! +--------+ | |! | ! | |!-- A_pcref | ! +--------+ | |! | D_enable ---!->| D_to_A |--> (analog enable ports) -->| |!-- A_gcref | ! +--------+ | |! | ! +-------+! | +===================================================+ | Model Unit consists of SPICE code plus A_to_D and D_TO_A converters | (references for D_to_A and A_to_D converters not shown) | | Figure 6: SPICE Model Unit, using an I/O buffer as an example | |============================================================================= | | KEYWORD DEFINITIONS: | |============================================================================= | Keyword: [External Model], [End External Model] | Required: No | Description: Used to reference an external file written in one of the | supported languages containing an arbitrary circuit | definition, but having ports that are compatible with the | [Model] keyword, or having ports that are compatible with | the [Model] keyword plus an additional signal port for true | differential buffers. | | Sub-Params: Language, Corner, Parameters, Ports, D_to_A, A_to_D | Usage Rules: The [External Model] keyword must be positioned within a | [Model] section and it may only appear once for each [Model] | keyword in a .ibs file. It is not permitted under the | [Submodel] keyword. | | [Circuit Call] may not be used to connect an [External Model]. | | A native IBIS [Model]'s data may be incomplete if the [Model] | correctly references an [External Model]. Any native IBIS | keywords that are used in such a case must contain syntactically | correct data and subparameters according to native IBIS rules. | In all cases, [Model]s which reference [External Model]s must | include the following keywords and subparameters: | | Model_type | Vinh, Vinl (as appropriate to Model_type) | [Voltage Range] and/or [Pullup Reference], | [Pulldown Reference], [POWER Clamp Reference], | [GND Clamp Reference], [External Reference] | | The following keywords and subparameters may be omitted, | regardless of Model_type, from a [Model] using [External Model]: | | C_comp and/or C_comp_* | [Ramp] | [Pulldown], [Pullup], [POWER Clamp], [GND Clamp] | | | Subparameter Definitions: | | | Language: | | Accepts "SPICE", "VHDL-AMS", or "Verilog-AMS" as arguments. | The Language subparameter is required and must appear only | once. | | | Corner: | | Three entries follow the Corner subparameter on each line: | | corner_name file_name circuit_name | | The corner_name entry is "Typ", "Min", or "Max". The | file_name entry points to the referenced file in the same | directory as the .ibs file. | | Up to three Corner lines are permitted. A "Typ" line is | required. If "Min" and/or "Max" data is missing, the tool | may use "Typ" data in its place. However, the tool should | notify the user of this action. | | The circuit_name entry provides the name of the circuit to | be simulated within the referenced file. For SPICE files, | this is normally a ".subckt" name. For VHDL-AMS files, this | is normally an "entity(architecture)" name pair. For | Verilog-AMS files, this is normally a "module" name. | | No character limits, case-sensitivity limits or extension | conventions are required or enforced for file_name and | circuit_name entries. However, the total number of | characters in each Corner line must comply with the rules in | Section 3. Furthermore, lower-case file_name entries are | recommended to avoid possible conflicts with file naming | conventions under different operating systems. Case | differences between otherwise identical file_name entries or | circuit_name entries should be avoided. External languages | may not support case-sensitive distinctions. | | | Parameters: | | Lists names of parameters that can be passed into an external | model file. Each Parameters assignment must match a name or | keyword in the external file or language. The list of | Parameters may span several lines by using the word | Parameters at the start of each line. The Parameters | subparameter is optional, and the external model must | operate with default settings without any Parameters | assignments. | | Parameter passing is not supported in SPICE. VHDL-AMS | parameters are supported using "generic" names, and | Verilog-AMS parameters are supported using "parameter" names. | | | Ports: | | Ports are interfaces to the [External Model] which are | available to the user and tool at the IBIS level. They are | used to connect the [External Model] to die pads. The | Ports parameter is used to identify the ports of the | [External Model] to the simulation tool. The port assignment | is by position and the port names do not have to match | exactly the names inside the external file. The list of | port names may span several lines if the word Ports is used | at the start of each line. | | Model units under [External Model] may only use reserved | ports. The reserved, pre-defined port names are listed in | the General Assumptions heading above. As noted earlier, | digital and analog reserved port functions will be assumed by | the tool and connections made accordingly. All the ports | appropriate to the particular Model_type subparameter entry | must be explicitly listed (see below). Note that the user | may connect SPICE models to A_to_D and D_to_A converters | using custom names for analog ports within the model unit, so | long as the digital ports of the converters use the digital | reserved port names. | | The rules for pad connections with [External Model] are | identical to those for [Model]. The [Pin Mapping] keyword | may be used with [External Model]s but is not required. If | used, the [External Model] specific voltage supply ports -- | A_puref, A_pdref, A_gcref, A_pcref and A_extref -- are | connected as defined under the [Pin Mapping] keyword. | In all cases, the voltage levels connected on the reserved | supply ports are defined by the [Power Clamp Reference], | [GND Clamp Reference], [Pullup Reference], [Pulldown | Reference] and/or [Voltage Range] keywords, as in the case | of [Model]. | | | Digital-to-Analog/Analog-to-Digital Conversions: | | These subparameters define all digital-to-analog and | analog-to-digital converters needed to properly connect | digital signals with the analog ports of referenced external | SPICE models. These subparameters must be used when | [External Model] references a file written in the SPICE | language. They are not permitted with Verilog-AMS or | VHDL-AMS external files. | | | D_to_A: | | As assumed in [Model], some interface ports of | [External Model] circuits expect digital input signals. As | SPICE models understand only analog signals, some conversion | from digital to analog format is required. For example, | input logical states such as '0' or '1,' implied in [Model], | must be converted to actual input voltage stimuli, such as a | voltage ramp, for SPICE simulation. | | The D_to_A subparameter provides information for converting | a digital stimulus, such as '0' or '1', into an analog | voltage ramp (a digital 'X' input is ignored by D_to_A | converters). Each digital port which carries data for | conversion to analog format must have its own D_to_A line. | | The D_to_A subparameter is followed by eight arguments: | | d_port port1 port2 vlow vhigh trise tfall corner_name | | The d_port entry holds the name of the digital. This entry is | used for the reserved port names D_drive, D_enable and D_switch. | The port1 and port2 entries hold the SPICE analog input port | names across which voltages are specified. These entries are | used for the user-defined port names, together with | another port name, used as a reference. | | Normally port1 accepts an input signal and port2 is the | reference for port1. However, for an opposite polarity | stimulus, port1 could be connected to a reference port and | port2 could serve as the input. | | The vlow and vhigh entries accept analog voltage values which | must correspond to the digital off and on states, where the | vhigh value must be greater than the vlow value. For | example, a 3.3 V ground-referenced buffer would list vlow as | 0 V and vhigh as 3.3 V. The trise and tfall entries are | times, must be positive and define input ramp rise and fall | times between 0 and 100 percent. | | The corner_name entry holds the name of the external model | corner being referenced, as listed under the Corner | subparameter. | | At least one D_to_A line must be present, corresponding to | the "Typ" corner model, for each digital line to be converted. | Additional D_to_A lines for other corners may be omitted. | In this case, the typical corner D_to_A entries will apply | to all model corners and the "Typ" corner_name entry may be | omitted. | | | A_to_D: | | The A_to_D subparameter is used to generate a digital state | ('0', '1', or 'X') based on analog voltages generated by | the SPICE model or analog voltages present at the pad/pin. | This allows an analog signal from the external SPICE circuit | or pad/pin to be read as a digital signal by the simulation | tool. | | The A_to_D subparameter is followed by six arguments: | | d_port port1 port2 vlow vhigh corner_name | | The d_port entry lists the reserved port name D_receive. As | with D_to_A, the port1 entry would normally contain the | reserved name A_signal (see below) or a user-defined port name, | while port2 may list any other analog reserved port name, used | as a reference. The voltage measurements are taken in this | example from the port1 entry with respect to the port2 | entry. These ports must also be named by the Ports | subparameter. | | The vlow and vhigh entries list the low and high analog | threshold voltage values. The reported digital state on | D_receive will be '0' if the measured voltage is lower than | the vlow value, '1' if above the vhigh value, and 'X' | otherwise. | | The corner_name entry holds the name of the external model | corner being referenced, as listed under the Corner | subparameter. | | At least one A_to_D line must be supplied corresponding to | the "Typ" corner model. Other A_to_D lines for other | corners may be omitted. In this case, the typical corner | A_to_D entries will apply to all model corners. | | IMPORTANT: measurements for receivers in IBIS are normally | assumed to be conducted at the die pads/pins. In such cases, | the electrical input model data comprises a "load" which | affects the waveform seen at the pads. However, for models | under [External Model], the user may choose whether to | measure the analog input response at the die pads or | inside the circuit (this does not preclude tools from | reporting digital D_receive and/or analog port responses in | addition to at-pad A_signal response). If at-pad | measurements are desired, the A_signal port would be named in | the A_to_D line under port1. The A_to_D converter then | effectively acts "in parallel" with the load of the circuit. | If internal measurements are desired (e.g., if the user | wishes to view the signal after processing by the receiver), | the user-defined signal port would be named in the | A_to_D line under port1. The A_to_D converter is effectively | "in series" with the receiver model. The vhigh and vlow | parameters should be adjusted as appropriate to the | measurement point of interest. | | Note that, while the port assignments and SPICE model must | be provided by the user, the D_to_A and A_to_D converters | will be provided automatically by the tool (the converter | parameters must still be declared by the user). There is no | need for the user to develop external SPICE code specifically | for these functions. | | A conceptual diagram of the port connections of a SPICE | [External Model] is shown below. The example illustrates an | I/O buffer. Note that the drawing implies that the D_receive | state changes in response to the analog signal my_receive, not | A_signal (see above): | | +-------------+ | | | | +------------+ | |--- A_puref | | |>--- my_drive ---->| | | D_drive -->| D_to_A | | | | | |---- my_ref -------| |--- A_pdref | +------------+ | | | | | | +------------+ | [External |--- A_pcref | | |>--- my_enable --->| Model] | | D_enable -->| D_to_A | | using | | | |---- A_gcref ------| SPICE |--- A_gcref | +------------+ | | | | | | +------------+ | |--- A_signal | | |<--- my_receive --<| | | D_receive -<| A_to_D | | | | | |---- my_ref -------| |--- A_extref | +------------+ | | | A_gnd ---| | | +-------------+ | | Figure 7: Example of an [External Model] I/O buffer using SPICE | | | An example of an [External Model] is shown at the end of | this section. | | | Pseudo-Differential Buffers: | | Pseudo-differential buffers may be described using a pair | of [External Model]s which may or may not be identical. | Each of the analog I/O signal ports (usually A_signal) is | connected to a specific pad through the [Pin] list in the usual | fashion, and the two ports are linked together as a differential | pair through the [Diff Pin] keyword. | | The reserved signal name A_signal is required for the I/O | signal ports of [External Model]s connected to pads used in a | pseudo-differential configuration. | | Users should note that, in pseudo-differential buffers, only | one formal signal port is used to stimulate the two [External | Model] digital inputs (D_drive). One of these inputs | will reflect the timing and polarity of the formal signal | port named by the user, while the other input is inverted and | (potentially) delayed with respect to the formal port as | defined under the [Diff Pin] keyword. THIS SECOND PORT IS | AUTOMATICALLY CREATED BY THE SIMULATION TOOL. Users do not | have to create special structures to invert or delay the | driven digital signal. Simulation tools will correctly | implement the two input ports once the [Diff Pin] keyword has | been detected in the .ibs file. This approach is identical | to that used in native IBIS. | | The D_to_A adapters used for SPICE files can be set up to | control ports on pseudo-differential buffers. If SPICE is | used as an external language, the [Diff Pin] vdiff | subparameter overrides the contents of vlow and vhigh under | A_to_D. | | IMPORTANT: For pseudo-differential buffers under [External | Model], the analog input response may only be measured | at the die pads. The [Diff Pin] parameter is required, and | controls both the polarity and the differential thresholds | used to determine the D_receive port response (the D_receive | port will follow the state of the non-inverting pin/pad as | referenced to the inverting pin/pad). For SPICE models, the | A_to_D line must name the A_signal port under either port1 | or port2, as with a single-ended buffer. The A_to_D | converter then effectively acts "in parallel" with the load | of the buffer circuit. The vhigh and vlow parameters will be | overridden by the [Diff Pin] vdiff declarations. | | The port relationships are shown in the examples below. | | +---------+ | | /| |--A_puref | | < |---+ |--A_pcref | | \| | |--A_gnd | +--------+ | | |--A_pdref | | |<-----------------------------+ |--A_extref | D_receive** -<| A_to_D | | | |--A_gcref | (ignored) | |---- my_ref ----------| | | | +--------+ | | | | | | | | +--------+ | |\ | | | | |>--- my_drive ------->| | \ | | | D_drive -->| D_to_A | | | >-+------A_signal | | |---- my_ref ----------| | / | (Non-inverting) | +--------+ | |/ | | | | | +--------+ | | | | |>--- my_enable ------>| | | D_enable*** ->| D_to_A | | | | | |---- A_pcref ---------| | | +--------+ +---------+ | | +---------+ | | | | | | | +--------+ | | | | |>--- my_enable ------>| |\ | | D_enable*** ->| D_to_A | | | \ | | | |---- A_pcref ---------| | >-+------A_signal | +--------+ | | / | | (Inverting) | my_drive* ------>| |/ | | | +--------+ | | |--A_puref | | |<-----------------------------+ |--A_pdref | D_receive** -<| A_to_D | | | |--A_pcref | (ignored) | |---- my_ref ----------| /| | |--A_gnd | +--------+ | < |-+ |--A_extref | | \| |--A_gcref | +---------+ | | Figure 8 - Example SPICE implementation | | * This signal is automatically created, by inverting and | delaying D_drive based on the information in [Diff Pin]. | | ** Pseudo-differential buffers must have A_to_D entries, | but D_receive is determined by the state of A_signal | (Inverting) and A_signal (Non-inverting) according to the | [Diff Pin] declaration. | | *** D_enable is shared between the separate buffers. This | sharing is handled by the EDA tool. | | | The following drawing illustrates the same concepts with a | *-AMS model. Note that the state of D_receive is determined | by the tool automatically by observing the A_signal ports. | The outputs of the actual receiver circuits in the *-AMS | models are not used for determining D_receive. | | +---------+ | D_receive** -------| |---A_puref | (ignored) | /| |---A_pcref | | < |---+ |---A_gnd | | \| | |---A_gcref | D_drive --||\ | |---A_pdref | || >----+-----A_signal (Non-inverting) | D_enable*** -------||/ | | | | | +---------+ | | +---------+ | | |---A_puref | D_enable*** -------||\ |---A_pcref | || >----+-----A_signal (Inverting) | (D_drive*) --||/ | |---A_gcref | | /| | |---A_pdref | | < |---+ |---A_gnd | | \| | | D_receive** -------| | | (ignored) +---------+ | | Figure 9 - Example *-AMS implementation | | * This signal is automatically created, by inverting and | delaying D_drive based on the information in [Diff Pin] | (digital output will be based on evaluation of signals %% and | && also using [Diff Pin]) | | ** D_receive for pseudo-differential buffers is determined by the | state of A_signal (Inverting) and A_signal (Non-inverting) | according to the [Diff Pin] declaration. | | *** D_enable is shared between the separate buffers. This sharing | is handled by the EDA tool. | | Two additional differential timing test loads are available: | | Rref_diff, Cref_diff | | These subparameters are also available under the [Model Spec] | keyword for typical, minimum, and maximum corners. | | These timing test loads require both sides of the | differential model to be operated. They can be used with the | existing timing test loads Rref, Cref, and Vref. The | existing timing test loads and Vmeas are used if Rref_diff | and Cref_diff are NOT given. | | | True Differential Models: | | True differential buffers may be described using [External | Model]. In a true differential [External Model], the | differential I/O ports which connect to die pads use the | reserved names A_signal_pos and A_signal_neg, as shown in the | diagram below. | | | +-----------+ | D_enable---| |---A_puref | ||\ |---A_pcref | D_drive----|| \----+---|---A_signal_pos | || /----|-+-|---A_signal_neg | ||/ /| | | |---A_gcref | | / |--+ | |---A_pdref | D_receive--| \ |----+ | | | \| |---A_gnd | | |---A_extref | +-----------+ | | Figure 10 | | | IMPORTANT: All true differential models under [External Model] | assume single-ended digital port connections (D_drive, | D_enable, D_receive). | | The [Diff Pin] keyword is still required within the same | [Component] definition when [External Model] describes a true | differential buffer. The models referenced by each pin listed | under [Diff Pin] MUST be the same. | | The D_to_A or A_to_D adapters used for SPICE files may be set | up to control or respond to true differential ports. An | example is shown below. | | | +--------+ +-----------+ | | |>--my_enable-->| |---A_puref | D_enable -->| D_to_A | | | | | |---my_ref------| |---A_pcref | +--------+ | | | ||\ | | +--------+ || \----+---+---A_signal_pos | | |>--my_drive -->|| /----|-+-+---A_signal_neg | D_drive -->| D_to_A | ||/ | | | | | |---my_ref------| | | | | +--------+ | | | |---A_gcref | | | | | | +--------+ | | | | | | |-----------------------+ | | | D_receive -<| A_to_D | | | | | | | |-------------------------+ | | +--------+ | | | | | | /| | | | | | / |--+ | |---A_pdref | | \ |----+ | | | \| |---A_gnd | | |---A_extref | +-----------+ | | Figure 11: Example SPICE implementation of a true differential buffer | | | If at-pad or at-pin measurement using a SPICE [External Model] | is desired, the vlow and vhigh entries under the A_to_D | subparameter must be consistent with the values of the [Diff | Pin] vdiff subparameter entry (the vlow value must | match -vdiff, | and the vhigh value must match +vdiff). The logic states | produced by the A_to_D conversion follow the same rules as for | single-ended buffers, listed above. An example is shown at the | end of this section. | | IMPORTANT: For true-differential buffers under [External | Model], the user can choose whether to measure the analog | input response at the die pads or internal to the circuit (this | does not preclude tools from reporting digital D_receive and/or | analog responses in addition to at-pad A_signal response). If | at-pad measurements for a SPICE model are desired, the | A_signal_pos port would be named in the A_to_D line under port1 | and A_signal_neg under port2. The A_to_D converter then | effectively acts "in parallel" with the load of the buffer | circuit. If internal measurements are desired (e.g., if the | user wishes to view the signal after processing by the input | buffer), the user-defined analog signal port would be named in | the A_to_D line under port1. The A_to_D converter is "in | series" with the receiver buffer model. The vhigh and vlow | parameters should be adjusted appropriate to the measurement | point of interest, so long as they as they are consistent with | the [Diff Pin] vdiff declarations. | | Note that the thresholds refer to the state of the non- | inverting signal, using the inverting signal as a reference. | Therefore, the output signal is considered high when, for | example, the non-inverting input is +200 mV above the inverting | input. Similarly, the output signal is considered low when the | same non- inverting input is -200 mV "above" the inverting | input. | | EDA tools will report the state of the D_receive port for true | differential *-AMS [External Model]s according to the AMS code | written by the model author; the use of [Diff Pin] does not | affect the reporting of D_receive in this case. EDA tools are | free to additionally report the state of the I/O pads according | to the [Diff Pin] vdiff subparameter. | | For both SPICE and *-AMS true differential [External | Model]s, the EDA tool must not override or change the | model author's connection of the D_receive port. | | Four additional Model_type arguments are available under the | [Model] keyword. One of these must be used when an [External | Model] describes a true differential model: | | I/O_diff, Output_diff, 3-state_diff, Input_diff | | Two additional differential timing test loads are available: | | Rref_diff, Cref_diff | | These subparameters are also available under the [Model Spec] | keyword for the typical, minimum, and maximum corner cases. | | These timing test loads require that both the inverting | and non-inverting ports of the differential model refer to | valid buffer model data (not terminations, supply rails, | etc.). The differential test loads may also be combined with | the single-ended timing test loads Rref, Cref, and Vref. | Note that the single-ended timing test loads plus Vmeas are | used if Rref_diff and Cref_diff are NOT supplied. | | | Series and Series Switch Models: | | Native IBIS did not define the transition characteristics of | digital switch controls. Switches were assumed to either be on | or off during a simulation and I-V characteristics could be | defined for either or both states. The [External Model] format | allows users to control the state of a switch through the | D_switch port. As with other digital ports, the use of SPICE | in an [External Model] requires the user to declare D_to_A | ports, to convert the D_switch signal to an analog input to | the SPICE model (whether the port's state may actually change | during a simulation is determined by the EDA tool used). | | Series and Series_switch devices both are described under the | [External Model] keyword using the reserved port names A_pos | and A_neg. Note that the [Series Pin Mapping] keyword must | be present and correctly used elsewhere in the file, in | order to properly set the logic state of the switch. | The A_pos port is defined in the first entry of the | [Series Pin Mapping] keyword, and the A_neg port is | defined in the pin2 entry. For series switches, the | [Series Switch Groups] keyword is required. | | | Ports required for various Model_types: | | As [External Model] makes use of the [Model] keyword's | Model_type subparameter, not all digital and analog reserved | ports may be needed for all Model_types. The table below | defines which reserved port names are required for various | Model_types. | | Model_type D_drive D_enable D_receive A_signal D_switch A_pos A_neg | | I/O* X X X X | 3-state* X X X | Output*, Open* X X | Input X X | Terminator X | Series X X | Series_switch X X X | | Model_type D_drive D_enable D_receive A_signal_pos A_signal_neg | | I/O_diff X X X X X | 3-state_diff X X X X | Output_diff X X X | Input_diff X X X | |----------------------------------------------------------------------------- | Example [External Model] using SPICE: |-------------------------------------- | [Model] ExBufferSPICE Model_type I/O Vinh = 2.0 Vinl = 0.8 | | Other model subparameters are optional | | typ min max [Voltage Range] 3.3 3.0 3.6 | [External Model] Language SPICE | | Corner corner_name file_name circuit_name (.subckt name) Corner Typ buffer_typ.spi buffer_io_typ Corner Min buffer_min.spi buffer_io_min Corner Max buffer_max.spi buffer_io_max | | Parameters - Not supported in SPICE | | Ports List of port names (in same order as in SPICE) Ports A_signal my_drive my_enable my_receive my_ref Ports A_puref A_pdref A_pcref A_gcref A_extref | | D_to_A d_port port1 port2 vlow vhigh trise tfall corner_name D_to_A D_drive my_drive my_ref 0.0 3.3 0.5n 0.3n Typ D_to_A D_enable my_enable A_gcref 0.0 3.3 0.5n 0.3n Typ | | A_to_D d_port port1 port2 vlow vhigh corner_name A_to_D D_receive my_receive my_ref 0.8 2.0 Typ | | Note: A_signal might also be used instead of a user-defined interface port | for measurements taken at the die pads | [End External Model] | |----------------------------------------- | Example [External Model] using VHDL-AMS: |----------------------------------------- | [Model] ExBufferVHDL Model_type I/O Vinh = 2.0 Vinl = 0.8 | | Other model subparameters are optional | | typ min max [Voltage Range] 3.3 3.0 3.6 | [External Model] Language VHDL-AMS | | Corner corner_name file_name circuit_name entity(architecture) Corner Typ buffer_typ.vhd buffer(buffer_io_typ) Corner Min buffer_min.vhd buffer(buffer_io_min) Corner Max buffer_max.vhd buffer(buffer_io_max) | | Parameters List of parameters Parameters delay rate Parameters preemphasis | | Ports List of port names (in same order as in VHDL-AMS) Ports A_signal A_puref A_pdref A_pcref A_gcref Ports D_drive D_enable D_receive | [End External Model] | |-------------------------------------------- | Example [External Model] using Verilog-AMS: |-------------------------------------------- | [Model] ExBufferVerilog Model_type I/O Vinh = 2.0 Vinl = 0.8 | | Other model subparameters are optional | | typ min max [Voltage Range] 3.3 3.0 3.6 | [External Model] Language Verilog-AMS | | Corner corner_name file_name circuit_name (module) Corner Typ buffer_typ.v buffer_io_typ Corner Min buffer_min.v buffer_io_min Corner Max buffer_max.v buffer_io_max | | Parameters List of parameters Parameters delay rate Parameters preemphasis | | Ports List of port names (in same order as in Verilog-AMS) Ports A_signal A_puref A_pdref A_pcref A_gcref Ports D_drive D_enable D_receive | [End External Model] | |----------------------------------------------------------- | Example of True Differential [External Model] using SPICE: |----------------------------------------------------------- | [Model] Ext_SPICE_Diff_Buff Model_type I/O_diff Rref_diff = 100 | | Other model subparameters are optional | | typ min max [Voltage Range] 3.3 3.0 3.6 | | [External Model] Language SPICE | | Corner corner_name file_name circuit_name (.subckt name) Corner Typ diffio.spi diff_io_typ Corner Min diffio.spi diff_io_min Corner Max diffio.spi diff_io_max | | Ports List of port names (in same order as in SPICE) Ports A_signal_pos A_signal_neg my_receive my_drive my_enable Ports A_puref A_pdref A_pcref A_gcref A_extref my_ref A_gnd | | D_to_A d_port port1 port2 vlow vhigh trise tfall corner_name D_to_A D_drive my_drive my_ref 0.0 3.3 0.5n 0.3n Typ D_to_A D_drive my_drive my_ref 0.0 3.0 0.6n 0.3n Min D_to_A D_drive my_drive my_ref 0.0 3.6 0.4n 0.3n Max D_to_A D_enable my_enable my_ref 0.0 3.3 0.5n 0.3n Typ D_to_A D_enable my_enable my_ref 0.0 3.0 0.6n 0.3n Min D_to_A D_enable my_enable my_ref 0.0 3.6 0.4n 0.3n Max | | A_to_D d_port port1 port2 vlow vhigh corner_name A_to_D D_receive A_signal_pos A_signal_neg -200m 200m Typ A_to_D D_receive A_signal_pos A_signal_neg -200m 200m Min A_to_D D_receive A_signal_pos A_signal_neg -200m 200m Max | [End External Model] | | |-------------------------------------------------------------- | Example of True Differential [External Model] using VHDL-AMS: |-------------------------------------------------------------- | [Model] Ext_VHDL_Diff_Buff Model_type I/O_diff Rref_diff = 100 | | typ min max [Voltage Range] 3.3 3.0 3.6 | | Other model subparameters are optional | [External Model] Language VHDL-AMS | | Corner corner_name file_name circuit_name entity(architecture) Corner Typ diffio_typ.vhd buffer(diff_io_typ) Corner Min diffio_min.vhd buffer(diff_io_min) Corner Max diffio_max.vhd buffer(diff_io_max) | | Parameters List of parameters Parameters delay rate Parameters preemphasis | | Ports List of port names (in same order as in VHDL-AMS) Ports A_signal_pos A_signal_neg D_receive D_drive D_enable Ports A_puref A_pdref A_pcref A_gcref | [End External Model] | |------------------------------------------------------------- | Example of Pseudo-Differential [External Model] using SPICE: |------------------------------------------------------------- | | Note that [Pin] and [Diff Pin] declarations are shown for clarity | | [Pin] signal_name model_name R_pin L_pin C_pin 1 Example_pos Ext_SPICE_PDiff_Buff 2 Example_neg Ext_SPICE_PDiff_Buff | | ... | [Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max 1 2 200mV 0ns 0ns 0ns | | ... | [Model] Ext_SPICE_PDiff_Buff Model_type I/O | | Other model subparameters are optional | | typ min max [Voltage Range] 3.3 3.0 3.6 | [External Model] Language SPICE | | Corner corner_name file_name circuit_name (.subckt name) Corner Typ diffio.spi diff_io_typ Corner Min diffio.spi diff_io_min Corner Max diffio.spi diff_io_max | | Ports List of port names (in same order as in SPICE) Ports A_signal my_drive my_enable my_ref Ports A_puref A_pdref A_pcref A_gcref A_gnd A_extref | | D_to_A d_port port1 port2 vlow vhigh trise tfall corner_name D_to_A D_drive my_drive my_ref 0.0 3.3 0.5n 0.3n Typ D_to_A D_drive my_drive my_ref 0.0 3.0 0.6n 0.3n Min D_to_A D_drive my_drive my_ref 0.0 3.6 0.4n 0.3n Max D_to_A D_enable my_enable A_pcref 0.0 3.3 0.5n 0.3n Typ D_to_A D_enable my_enable A_pcref 0.0 3.0 0.6n 0.3n Min D_to_A D_enable my_enable A_pcref 0.0 3.6 0.4n 0.3n Max | | A_to_D d_port port1 port2 vlow vhigh corner_name A_to_D D_receive A_signal my_ref 0.8 2.0 Typ A_to_D D_receive A_signal my_ref 0.8 2.0 Min A_to_D D_receive A_signal my_ref 0.8 2.0 Max | | This example shows the evaluation of the received signals at the die | pads. [Diff Pin] defines the interpretation of the A_to_D output | polarity and levels and overrides the A_to_D settings shown above. | [End External Model] | |============================================================================= | Keyword: [External Circuit], [End External Circuit] | Required: No | Description: Used to reference an external file containing an arbitrary | circuit description using one of the supported languages. | Sub-Params: Language, Corner, Parameters, Ports, D_to_A, A_to_D | Usage Rules: Each [External Circuit] keyword must be followed by a unique | name that differs from any name used for any [Model] or | [Submodel] keyword. | | The [External Circuit] keyword may appear multiple times. It | is not scoped by any other keyword. | | Each instance of an [External Circuit] is referenced by one | or more [Circuit Call] keywords discussed later. (The | [Circuit Call] keyword cannot be used to reference a | [Model] keyword.) | | The [External Circuit] keyword and contents may be placed | anywhere in the file, outside of any [Component] keyword | group or [Model] keyword group, in a manner similar to that | of the [Model] keyword. | | | Subparameter Definitions: | | | Language: | | Accepts "SPICE", "VHDL-AMS", or "Verilog-AMS" as arguments. | The Language subparameter is required and may appear only | once. | | | Corner: | | Three entries follow the Corner subparameter on each line: | | corner_name file_name circuit_name | | The corner_name entry is "Typ", "Min", or "Max". The | file_name entry points to the referenced file in the same | directory as the .ibs file. | | Up to three Corner lines are permitted. A "Typ" line is | required. If "Min" and/or "Max" data is missing, the tool | may use "Typ" data in its place. However, the tool should | notify the user of this action. | | The circuit_name entry provides the name of the circuit to | be simulated within the referenced file. For SPICE files, | this is normally a ".subckt" name. For VHDL-AMS files, this | is normally an "entity(architecture)" name pair. For | Verilog-AMS files, this is normally a "module" name. | | No character limits, case-sensitivity limits or extension | conventions are required or enforced for file_name and | circuit_name entries. However, the total number of characters | in each Corner line must comply with Section 3. Furthermore, | lower-case file_name entries are recommended to avoid | possible conflicts with file naming conventions under | different operating systems. Case differences between | otherwise identical file_name entries or circuit_name entries | should be avoided. External languages may not support | case-sensitive distinctions. | | | Parameters: | | Lists names of parameters that may be passed into an external | circuit file. Each Parameters assignment must match a name or | keyword in the external file or language. The list of | Parameters can span several lines by using the word | Parameters at the start of each line. The Parameters | subparameter is optional, and the external circuit must | operate with default settings without any Parameters | assignments. | | Parameter passing is not supported in SPICE. VHDL-AMS | parameters are supported using "generic" names, and | Verilog-AMS parameters are supported using "parameter" names. | | | Ports: | | Ports are interfaces to the [External Model] which are | available to the user and tool at the IBIS level. They are | used to connect the [External Model] to die pads. The | Ports parameter is used to identify the ports of the | [External Model] to the simulation tool. The port assignment | is by position and the port names do not have to match | exactly the names inside the external file. The list of | port names may span several lines if the word Ports is used | at the start of each line. | | The Ports parameter is used to | identify the ports of the [External Circuit] to the simulation | tool. The port assignment is by position and the port names | do not have to match exactly the port names in the external | file. The list of port names may span several lines if the | word Ports is used at the start of each line. | | [External Circuit] allows any number of ports to be defined, | with any names which comply with Section 3 format requirements. | Reserved port names may be used, but ONLY DIGITAL PORTS will | have the pre-defined functions listed in the General | Assumptions heading above. User-defined and reserved | port names may be combined within the same [External Circuit]. | | The [Pin Mapping] keyword cannot be used with [External | Circuit] in the same [Component] description. | | | Digital-to-Analog/Analog-to-Digital Conversions: | | These subparameters define all digital-to-analog and | analog-to-digital converters needed to properly connect | digital signals with the analog ports of referenced external | SPICE models. These subparameters must be used when | [External Circuit] references a file written in the SPICE | language. They are not permitted with Verilog-AMS or VHDL-AMS | external files. | | | D_to_A: | | As assumed in [Model] and [External Model], some | interface ports of [External Circuit]s expect digital input | signals. As SPICE models understand only analog signals, | some conversion from digital to analog format is required. | For example, input logical states such as '0' or '1' must | be converted to actual input voltage stimuli, such as a | voltage ramp, for SPICE simulation. | | The D_to_A subparameter provides information for converting | a digital stimulus, such as '0' or '1', into an analog | voltage ramp (a digital 'X' input is ignored by D_to_A | converters). Each digital port which carries data for | conversion to analog format must have its own D_to_A | declaration. | | The D_to_A subparameter is followed by eight arguments: | | d_port port1 port2 vlow vhigh trise tfall corner_name | | The d_port entry holds the name of the digital port. This entry | may contain user-defined port names or the reserved port names | D_drive, D_enable and D_switch. The port1 and port2 entries | hold the SPICE analog input port names across which voltages are | specified. These entries contain user-defined port names. One | of these port entries must name a reference for the other port | (for example, A_gnd). | | Normally, port1 accepts an input signal and port2 is the | reference for port1. However, for an opposite polarity | stimulus, port1 could be connected to a voltage reference and | port2 could serve as the input. | | The vlow and vhigh entries accept voltage values which | correspond to fully-off and fully-on states, where the vhigh | value must be greater than the vlow value. For example, a | 3.3 V ground-referenced buffer would list vlow as 0 V and | vhigh as 3.3 V. The trise and tfall entries are times, must | be positive and define input ramp rise and fall times | between 0 and 100 percent. | | The corner_name entry holds the name of the external circuit | corner being referenced, as listed under the Corner | subparameter. | | Any number of D_to_A subparameter lines is allowed, so long | as each contains a unique port_name entry and at least one | unique port1 or port2 entry (i.e., several D_to_A | declarations may use the same reference node under port1 or | port2). At least one D_to_A line must be present, | corresponding to the "Typ" corner model, for each digital | line to be converted. Additional D_to_A lines for other | corners may be omitted. In this case, the typical corner | D_to_A entries will apply to all model corners and the | "Typ" corner_name entry may be omitted. | | | A_to_D: | | The A_to_D subparameter is used to generate a digital state | ('0', '1', or 'X') based on analog voltages from the SPICE model | or from the pad/pin. This allows an analog signal from the | external SPICE circuit to be read as a digital signal by the | simulation tool. Each analog port which carries data for | conversion to digital format must have its own A_to_D | declaration line. | | The A_to_D subparameter is followed by six arguments: | | d_port port1 port2 vlow vhigh corner_name | | The d_port entry lists port names to be used for digital | signals going. As with D_to_A, the port1 entry | would contain a user-defined analog signal. Port2 would list | another port name to be used as a reference. The voltage | measurements are taken from the port1 entry with respect to | the port2 entry. These ports must also be named by the Ports | subparameter. | | The vlow and vhigh entries list the low and high analog | threshold voltage values. The reported digital state on | D_receive will be '0' if the measured voltage is lower than | the vlow value, '1' if above the vhigh value, and 'X' | otherwise. | | The corner_name entry holds the name of the external model | corner being referenced, as listed under the Corner | subparameter. | | Any number of A_to_D subparameter lines is allowed, so long | as each contains a unique port_name entry and at least one | unique port1 or port2 entry (i.e., several A_to_D declarations | may use the same reference node under port1 or port2). For | example, a user may wish to create additional A_to_D | converters for individual analog signals to monitor common | mode behaviors on differential buffers (see below). | | At least one A_to_D line must be supplied corresponding to | the "Typ" corner model. Other A_to_D lines for other | corners may be omitted. In this case, the typical corner | D_to_A entries will apply to all model corners. | | IMPORTANT: measurements for receivers in IBIS may be conducted | at the die pads or the pins. In such cases, | the electrical input model data comprises a "load" which | affects the waveform seen. However, for | [External Circuit]s, the user may choose whether to | measure the analog input response in the usual fashion or | internal to the circuit (this does not preclude tools from | reporting digital D_receive and/or analog responses | in addition to normal A_signal response). If native IBIS | measurements are desired, the A_signal port would be named in | the A_to_D line under port1. The A_to_D converter then | effectively acts "in parallel" with the load of the circuit. | If internal measurements are desired (e.g., if the user | wishes to view the signal after processing by the receiver), | the user-defined analog signal port would be named | in the A_to_D line under port1. The A_to_D converter is | effectively "in series" with the receiver model. The vhigh | and vlow parameters should be adjusted appropriate to the | measurement point of interest. | | Note that, while the port assignments and SPICE model data | must be provided by the user, the D_to_A and A_to_D converters | will be provided automatically by the tool. There is no need | for the user to develop external SPICE code specifically for | these functions. | | The [Diff Pin] keyword is NOT required for true differential | [External Circuit] descriptions. | | Pseudo-differential buffers are not supported under [External | Circuit]. Use the existing [Model] and [External Model] | keywords to describe these structures. | | Note that the EDA tool is responsible for determining the | specific measurement points for reporting timing and signal | quality for [External Circuit]s. | | In all other respects, [External Circuit] behaves exactly as | [External Model]. | |----------------------------------------------------------------------------- | Model B as an [External Circuit] |---------------------------------------- | Example [External Circuit] using SPICE: |---------------------------------------- | [External Circuit] BUFF-SPICE Language SPICE | | Corner corner_name file_name circuit_name (.subckt name) Corner Typ buffer_typ.spi bufferb_io_typ Corner Min buffer_min.spi bufferb_io_min Corner Max buffer_max.spi bufferb_io_max | | Parameters - Not supported in SPICE | | Ports List of port names (in same order as in SPICE) Ports A_signal int_in int_en int_out A_control Ports A_puref A_pdref A_pcref A_gcref | | D_to_A d_port port1 port2 vlow vhigh trise tfall corner_name D_to_A D_drive int_in my_gcref 0.0 3.3 0.5n 0.3n Typ D_to_A D_drive int_in my_gcref 0.0 3.0 0.6n 0.3n Min D_to_A D_drive int_in my_gcref 0.0 3.6 0.4n 0.3n Max D_to_A D_enable int_en my_gnd 0.0 3.3 0.5n 0.3n Typ D_to_A D_enable int_en my_gnd 0.0 3.0 0.6n 0.3n Min D_to_A D_enable int_en my_gnd 0.0 3.6 0.4n 0.3n Max | | A_to_D d_port port1 port2 vlow vhigh corner_name A_to_D D_receive int_out my_gcref 0.8 2.0 Typ A_to_D D_receive int_out my_gcref 0.8 2.0 Min A_to_D D_receive int_out my_gcref 0.8 2.0 Max | | Note, the A_signal port might also be used and int_out not defined in | a modified .subckt. | [End External Circuit] | |------------------------------------------- | Example [External Circuit] using VHDL-AMS: |------------------------------------------- | [External Circuit] BUFF-VHDL Language VHDL-AMS | | Corner corner_name file_name circuit_name entity(architecture) Corner Typ buffer_typ.vhd bufferb(buffer_io_typ) Corner Min buffer_min.vhd bufferb(buffer_io_min) Corner Max buffer_max.vhd bufferb(buffer_io_max) | | Parameters List of parameters Parameters delay rate Parameters preemphasis | | Ports List of port names (in same order as in VHDL-AMS) Ports A_signal A_puref A_pdref A_pcref A_gcref A_control Ports D_drive D_enable D_receive | [End External Circuit] | |---------------------------------------------- | Example [External Circuit] using Verilog-AMS: |---------------------------------------------- | [External Circuit] BUFF-VERILOG Language Verilog-AMS | | Corner corner_name file_name circuit_name (module) Corner Typ buffer_typ.v bufferb_io_typ Corner Min buffer_min.v bufferb_io_min Corner Max buffer_max.v bufferb_io_max | | Parameters List of parameters Parameters delay rate Parameters preemphasis | | Ports List of port names (in same order as in Verilog-AMS) Ports A_signal A_puref A_pdref A_pcref A_gcref A_control Ports D_drive D_enable D_receive | [End External Circuit] | | Interconnect Structure as an [External Circuit] | |---------------------------------------- | Example [External Circuit] using SPICE: |---------------------------------------- | [External Circuit] BUS_SPI Language SPICE | | Corner corner_name file_name circuit_name (.subckt name) Corner Typ bus_typ.spi Bus_typ Corner Min bus_min.spi Bus_min Corner Max bus_max.spi Bus_max | | Parameters - Not supported in SPICE | | Ports are in same order as defined in SPICE Ports vcc gnd io1 io2 Ports int_ioa vcca1 vcca2 vssa1 vssa2 Ports int_iob vccb1 vccb2 vssb1 vssb2 | | No A_to_D or D_to_A required, as no digital ports are used | [End External Circuit] | |------------------------------------------- | Example [External Circuit] using VHDL-AMS: |------------------------------------------- | [External Circuit] BUS_VHD Language VHDL-AMS | | Corner corner_name file_name circuit_name entity(architecture) Corner Typ bus.vhd Bus(Bus_typ) Corner Min bus.vhd Bus(Bus_min) Corner Max bus.vhd Bus(Bus_max) | | Parameters List of parameters Parameters r1 l1 Parameters r2 l2 temp | | Ports are in the same order as defined in VHDL-AMS Ports vcc gnd io1 io2 Ports int_ioa vcca1 vcca2 vssa1 vssa2 Ports int_iob vccb1 vccb2 vssb1 vssb2 | |---------------------------------------------- | Example [External Circuit] using Verilog-AMS: |---------------------------------------------- | [External Circuit] BUS_V Language Verilog-AMS | | Corner corner_name file_name circuit_name (module) Corner Typ bus.v Bus_typ Corner Min bus.v Bus_min Corner Max bus.v Bus_max | | Parameters List of parameters Parameters r1 l1 Parameters r2 l2 temp | | Ports are in the same order as defined in Verilog-AMS Ports vcc gnd io1 io2 Ports int_ioa vcca1 vcca2 vssa1 vssa2 Ports int_iob vccb1 vccb2 vssb1 vssb2 | [End External Circuit] | |============================================================================= | The scope of the following keywords is limited to the [Component] keyword. They apply to the specific set of pin numbers and internal nodes only within that [Component]. | |============================================================================= | Keyword: [Node Declarations], [End Node Declarations] | Required: Yes, if any internal nodes exist on the die as listed in | [Circuit Call], and/or if any die pads need to be explicitly | defined. | Description: Provides a list of internal die nodes and/or die pads for a | [Component] to make unambiguous interconnection descriptions | possible. | Usage Rules: All die node and die pad names that appear under any [Circuit | Call] keyword within the same [Component] must be listed | under the [Node Declarations] keyword. | | If used, the [Node Declarations] keyword must appear before | any [Circuit Call] keyword(s) under the [Component] keyword. | Only one [Node Declarations] keyword is permitted for each | [Component] keyword. Since the [Node Declarations] keyword | is part of the [Component] keyword, all internal node or pad | references apply only to that [Component] (i.e. they are | local). | | The internal die node and/or die pad names within [Node | Declarations] must be unique and therefore different from | the pin names used in the [Pin] keyword. Each node and/or | pad name must be separated by at least one white space. The | list may span several lines and is terminated by the [End | Node Declarations] keyword. | | The names of die nodes and die pads can be composed of any | combination of the legal characters outlined in Section 3. |----------------------------------------------------------------------------- [Node Declarations] | Must appear before any [Circuit Call] keyword | | Die nodes: a b c d e | List of die nodes f g h nd1 | | Die pads: pad_2a pad_2b pad_4 pad_11 | List of die pads | [End Node Declarations] | |============================================================================= | Keyword: [Circuit Call], [End Circuit Call] | Required: Yes, if any [External Circuit]s are present in a [Component]. | Description: This keyword is used to instantiate [External Circuit]s and | to connect their ports to the die nodes or die pads. | Sub-Params: Signal_pin, Diff_signal_pins, Series_pins, Port_map | Usage Rules: The [Circuit Call] keyword must be followed by the name of | an [External Circuit] that exists in the same [Component]. | | When a [Circuit Call] keyword defines any connections that | involve one or more die pads (and consequently pins), the | corresponding pins on the [Pin] list must use the reserved | word "CIRCUITCALL" in the third column instead of a model | name. | | Each [External Circuit] must have at least one corresponding | [Circuit Call] keyword. Multiple [Circuit Call] keywords may | appear under a [Component] using the same [External Circuit] | name, if multiple instantiations of an [External Circuit] | are needed. | | | Signal_pin, Diff_signal_pins, or Series_pins: | | The purpose of these subparameters is to identify which | [External Circuit] needs to be stimulated in order to obtain | a signal on a certain pin. These subparameters must be used | only when the [External Circuit] that is referenced by the | [Circuit Call] keyword has an effect on a pin. Only one of | the three subparameters is permitted in a given [Circuit | Call] keyword. The subparameters are followed by one or two | pin names which are defined by the [Pin] keyword. | | Signal_pin is used when the referenced [External Circuit] | has a single analog signal port (I/O) connection to one pin. | The subparameter is followed by a pin name that must match | one of the pin names under the [Pin] keyword. | | Diff_signal_pins is used when the referenced [External | Circuit] describes a true differential model which has two | analog signal port (I/O) connections, each to a separate | pin. The subparameter is followed by two pin names, each of | which must match one of the pin names under the [Pin] | keyword. The first and second pin names correspond to the | non-inverting and inverting signals of the differential | model, respectively. The two pin names must not be | identical. | | Series_pins is used when the referenced [External | Circuit] describes a Series or Series_switch model which | has two analog signal port (I/O) connections to two pins. | The subparameter is followed by two pin names, each of which | must match one of the pin names under the [Pin] keyword. The | first and second pin names correspond to the positive and | negative ports of the Series or Series_switch model, | respectively. However, the polarity order matters only when | the model is polarity sensitive (as with the [Series | Current] keyword). The two pin names must not be identical. | | | Port_map: | | The Port_map subparameter is used to connect the ports of an | [External Circuit] to die nodes or die pads. | | Every occurrence of the Port_map subparameter must begin on a | new line and must be followed by two arguments, the first | being a port name, and the second being a die node, die pad, | or a pin name. | | The first argument of Port_map must contain a port name that | matches one of the port names in the corresponding [External | Circuit] definition. No port name may be listed more than | once within a [Circuit Call] statement. Only those port | names need to be listed with the Port_map subparameter which | are connected to a die node or a die pad. This includes | reserved and/or user-defined port names. | | The second argument of the Port_map subparameter contains | the name of a die node, die pad, or a pin. The names of die | nodes, die pads, and pins may appear multiple times as | Port_map subparameter arguments within the same [Circuit | Call] statement to signify a common connection between | multiple ports, such as common voltage supply. | | Please note that a pin name in the second argument does not | mean that the connection is made directly to the pin. Since | native IBIS does not have a mechanism to declare die pads | explicitly, connections to die pads are made through their | corresponding pin names (listed under the [Pin] keyword). | This convention must only be used with native IBIS package | models where a one-to-one path between the die pads and pins | is assumed. When a package model other than native IBIS is | used with a [Component], the second argument of Port_map | must have a die pad or die node name. These names are | matched to the corresponding port name of the non-native | package model by name (not by position). In this case, the | package model may have an arbitrary circuit topology between | the die pads and the pins. A one-to-one mapping is not | required. |----------------------------------------------------------------------------- | Examples: |----------------------------------------------------------------------------- | | For the examples below please refer to the following diagram and the | example provided for the [Node Declarations] keyword. | | Component Die Package Pins/balls |-------------------------------------------------------+ +-------+ | | | | | [E.Circuit] [E.Circuit] | | | | +-------------------------+ +--------------+ | | | | | Model_A A_mypcr-+-a-+-vcca1 vcc-+-10-----+-+--@@@--o 10 Vcc | | |\ A_mypur-+-b-+-vcca2 | | | | | |D_drive--| >---+-A_mysig-+-c-+-int_ioa io1-+-1------+-+--@@@--o 1 Buffer A | |D_enable-|/ /| | A_mypdr-+-d-+-vssa1 | | | | | |D_receive--< |-+ A_mygcr-+-e-+-vssa2 gnd-+-pad_11-+-+--@@@--o 11 GND | | \| | | | | | | | +-------------------------+ | Die_ | | | | | | Interconnect | | | | | [E.Circuit] | | | | | | +-------------------------+ | | | | | | | Model_B | | | | | | | | |\ A_mypur-+-f-+-vccb1 | | | | Self Ad- | |D_drive--| >-----A_mysig-+-g-+-int_ob o2-+-pad_2a-+-+-@@@-+-o 2 justing | | |/ A_mypdr-+-h-+-vssb1 | | | | | Buffer | | |A_mycnt | | | | | | | | +----------+--------------+ +--------------+ | | | | | | Analog Buffer Control | | | | | +-----------------------------------pad_2b-+-+-@@@-+ | | | | | | [E.Circuit] | | | | +--------------------------+ | | | | | Model_C A_mypcr-+-10---(to pin/pad 10) | | | | | |\ A_mypur-+-10---(to pin/pad 10) | | | | nd1-+-D_mydrv--| >---+-A_mysig-+-3--------------------+-+--@@@--o 3 Buffer C | | | D_enable-|/ /| | A_mypdr-+-pad_11 | | | | | | D_receive--< |-+ A_mygcr-+-pad_11 | | | | | | \| | | | | | | +--------------------------+ | | | | | | | | | | [E.Circuit] | | | | | +--------------------------+ | | | | | | Model_D | | | | | | | /| A_mypcr-+-10---(to pin/pad 10) | | +-@@@-o 4a Clocka | nd1-+-D_receive--< |---A_mysig-+-pad_4----------pad_4-+-+-+ | | | \| A_mygcr-+-pad_11 | | +-@@@-o 4b Clockb | +--------------------------+ | | | | | | | | [E.Model] inside [Model] | | | | +-----------------------------+ | | | | | Model_E A_pcref-+-> | | | | | |\ A_puref-+-> | | | | | D_drive--| >---+---A_signal-+-------------------+-+--@@@--o 5 Buffer E | | D_enable-|/ /| | A_pdref-+-> | | | | | D_receive--< |-+ A_gcref-+-> | | | | | \|---A_external-+-> | | | | | A_gnd-+-> | | | | +-----------------------------+ | | | |-------------------------------------------------------+ +-------+ | | Notes: | 1) The ports of the [External Model] Model_E are automatically connected by | the tool, taking the [Pin Mapping] keyword into consideration, if exists. | 2) The package model shown in this drawing assumes the capabilities of a | non-native IBIS package model are available to the model author. | | Figure 12 | | [Circuit Call] Model_A | Instantiates [External Circuit] named "A" | Signal_pin 1 | | mapping port pad/node | Port_map A_mypcr a | Port to internal node connection Port_map A_mypur b | Port to internal node connection Port_map A_mysig c | Port to internal node connection Port_map A_mypdr d | Port to internal node connection Port_map A_mygcr e | Port to internal node connection | [End Circuit Call] | | [Circuit Call] Model_B | Instantiates [External Circuit] named "B" | Signal_pin 2 | | mapping port pad/node | Port_map A_mypur f | Port to internal node connection Port_map A_mysig g | Port to internal node connection Port_map A_mypdr h | Port to internal node connection Port_map A_mycnt pad_2b | Port to explicit pad connection | [End Circuit Call] | | [Circuit Call] Model_C | Instantiates [External Circuit] named "C" | Signal_pin 3 | | mapping port pad/node | Port_map A_mypcr 10 | Port to implicit pad connection Port_map A_mypur 10 | Port to implicit pad connection Port_map A_mysig 3 | Port to implicit pad connection Port_map A_mypdr pad_11 | Port to explicit pad connection Port_map A_mygcr pad_11 | Port to explicit pad connection Port_map D_mydrv nd1 | Port to internal node connection | [End Circuit Call] | | [Circuit Call] Model_D | Instantiates [External Circuit] named "D" | Signal_pin 4a | | mapping port pad/node | Port_map A_my_pcref 10 | Port to implicit pad connection Port_map A_my_signal pad_4 | Port to explicit pad connection Port_map A_my_gcref pad_11 | Port to explicit pad connection Port_map D_receive nd1 | Port to internal node connection | [End Circuit Call] | | [Circuit Call] Die_Interconnect | Instantiates [External Circuit] named | "Die_Interconnect" | | mapping port pad/node | Port_map vcc 10 | Port to implicit pad connection Port_map gnd pad_11 | Port to explicit pad connection Port_map io1 1 | Port to implicit pad connection Port_map o2 pad_2a | Port to explicit pad connection Port_map vcca1 a | Port to internal node connection Port_map vcca2 b | Port to internal node connection Port_map int_ioa c | Port to internal node connection Port_map vssa1 d | Port to internal node connection Port_map vssa2 e | Port to internal node connection Port_map vccb1 f | Port to internal node connection Port_map int_ob g | Port to internal node connection Port_map vssb1 h | Port to internal node connection | [End Circuit Call] | ****************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: The IBIS-X Macro-language activity is addressing the extended model behavior problem. However, its solution depends upon a new syntactical macro-language which will take time to debug and implement. While a single, common macro-language is highly desirable, An alternative, simpler, shorter term path that leverages off industrially accepted public formats and standards will also address the industrial needs in a very IBIS compatible manner. Two types of languages that lend themselves to extending IBIS: SPICE and various hardware description languages with analog/mixed signal extensions. While either type of language can be used for all extensions, SPICE formats are particularly strong for electrical interconnect extensions and structural device descriptions while the hardware description languages are particularly strong in equation handling and behavioral/logical extensions. At this time Berkeley SPICE, VHDL-AMS and Verilog-AMS are the proposed targeted extension languages. This is based on several desirable criteria: Applicable to electrical circuit, device, and modeling issues Open, publicly available format Widely used, either directly or through emulation Controlled under an official standardization group or independent body Language is stable and is expected to remain downward compatible The official IBIS list should not include vendor-specific implementations, extensions, or deviations even if they are widely used. Vendors can deal this issue by non-compliant IBIS extensions or interpretations. These criteria are intended to limit the support of many language formats (especially private de facto formats) to maximize model interoperability. Berkeley level 3F5, VHDL-AMS and related extensions, and Verilog-AMS appear to meet the above criteria. Verilog-AMS is still being processed for formal IEEE standardization. So, the reference recognizes that the language call will eventually mean the full, officially approved version. Berkeley SPICE 3F5 is no longer readily available. However, it has served as the basis of a number of commercial implementations that it still serves as a SPICE baseline reference. Berkeley SPICE 2G6 could also have served as a base, but it contains numerical node naming restrictions and other restrictions that are not seen in practice. External language syntax is not embedded within .ibs files because in most tools such syntax would have to be exported into separate files in order for the EDA tool to test and process it without syntactical errors. BIRD75 was reviewed by the IBIS Futures Working Group, and a number of choices already resolved are reflected in this BIRD75. Two Registration choices are given for discussion. Description 1 supports possible future EBD style syntactical expansion where several models can be associated with a die node (pin). Description 2 supports existing IBIS conventions with a tight association of a specific model_name to a pin number, even if there are added electrical paths on the die. BIRD75.1 has some editorial corrections. The Registration option below is captured |* |* Description 1 |* | REGISTERING MODELS: | | The [Pin] keyword subparameter model_name is used to register [Model]s and | signify a direct connection to the die node. However, the model_name entry | must be NC when a model or any part of it is connected by the [Circuit Call] | keyword. Normally, this convention is used to distinguish direct die node | connections from indirect die node connections that occur through paths | given by the [External Circuit] keyword. However, NC can also be optionally | used with [Circuit Call] even if the connections (A_signal* ports) are made | directly to the die nodes. The [Circuit Call] keyword provides both the | model_name and Cell_port (or Diff_cell_port) die nodes, so NC is entered | under the [Pin] keyword to avoid redundant information. | |----------------------------------------------------------------------------- | Example of Registration: | [Pin] signal_name model_name R_pin L_pin C_pin | 1 A NC | Models A and B are connected through [External 2 B NC | Circuit] and [Circuit Call] keywords 3 Control_pin NC | Control_pin connection is though [Circuit Call] | ... | to a circuit outside of the component 10 POWER POWER 11 GND GND | ... |----------------------------------------------------------------------------- The futures group stated that they preferred the model name in the pin list, even if it is redundant. BIRD75.1 documents this is Description 2. BIRD75.2: BIRD75.2 makes some editorial changes suggested by Arpad Muranyi and others. Also several [Circuit Call] subparameters are renamed to better reflect the association of a model to a particular pin (or corresponding die node): Cell_port to Signal_pin Diff_cell_port to Diff_signal_pins Series_cell_port to Series_pins BIRD75.2 also changes from BIRD75.1 the Timing_location and SI_location "Die" specification to mean the die node side of the package model (rather than the A_signal* location on the model. This is consistent with the existing definition and with die measurement techniques. More consideration is done for true differential buffers when using [External Model]. The additions include: Four new Model_type entries: I/O_diff, Output_diff, Input_diff, 3-state_diff and two new differential timing test loads: Rref_diff, Cref_diff These are also added to the [Model Spec] subparameter list for possible typ/min/max variations. The rules for the *_diff model types will be changed: [Diff Pin] is required, not optional for true differential model The models on each pin must be identical (not so for single-ended constructions) The *_diff timing test loads are used under differential conditions The single-ended timing test loads Vref, Rref, Cref are still permitted without the *_diff timing test loads or in combination with *_diff And, the *_diff timing test loads can be used with single-ended construction of differential buffers. The predefined signals A_signal_p and A_signal_n are changed to A_signal_pos and A_signal_neg for clarity. These changes are made for clarity, consistency with IBIS and expansion. Also, a case is given using the predefined reference signals where the [External Model] can be set up with external voltages that are defined for typ/min/max cases by the IBIS Keywords [Voltage Range] or the [Pullup Reference], [Pulldown Reference], [Power Clamp Reference], and [Gnd Clamp Reference] keywords. This is added to let the existing IBIS voltage columns be used to provide typ/min/max voltages on models under with existing IBIS controls. The predefined port names for voltage reference terminals support this addition. In addition, because six new subparameters are introduced as keywords under existing IBIS, the pending IBIS Version 4.0 document needs to show the specific subparameter additions to the [Model] and [Model Spec] keywords. Since BIRD75.2 is already very long, a new BIRD77 will be introduced separately to show changes in the IBIS Version 4.0 document for these existing keywords. Both BIRD75.2 and BIRD77 need to be considered together. BIRD75.3: As a result of the August 9, 2002 meeting and private responses, a number of clarification improvements have been made as noted by |*** lines. BIRD75.4: BIRD75.4 is issued in response to the August 30, 2002 meeting comments. The major addition was to propose as syntax for parameterization. This is accomplished by a new subparameter "Parameters" under both the [External Circuit] and [External Model] keywords. This would only be supported in VHDL-AMS and Verilog-AMS since (Berkeley) SPICE does not support a method that is used by several vendor-specific SPICEs. The method proposes parameter values as quoted strings because there can be spaces in some languages ("1.0 ns") and unique format conventions and case sensitivity/insensitivity rules in others. The parameters are required to be passed according to the formatting rules of the external language. Also, the methods to connect reference supplies to external models is clarified. The [Ramp] keyword is now added to the list of required keywords when [External Model] is present for I/O*, Output*, 3-state* and Open* model types. While [Ramp] would not be used for buffer simulation, it is often used in tools to get an estimate of the pulse duration for timing tests in existing IBIS. So the [Ramp] requirement is retained. No change was made at this time with respect to the positioning of [External Model]. Some concerns were not addressed because I did not fully understand the issues. These are documented with |**** lines. BIRD75.5 Editorial changes are made in response to the September 20, 2002 comments and are documented by |***** lines. These changes include clarifying that the [External Circuit] can be used for any type of passive or active circuit and does not have to be associated with a [Model]. BIRD75.6 More changes, suggested by Michael Mirmak and Arpad Muranyi (privately) are made and noted by |*6 comments. BIRD75.7 BIRD75.7 is a complete rewrite of BIRD75.6, thanks to Michael Mirmak and Arpad Muranyi. As a result it is better organized, more readable, and contains many more examples. Arpad Muranyi, Michael Mirmak, and Chris Reid have joined as co-authors since all have contributed to helping clarify some major points. This rewrite was prompted by a number of technical concerns and discussions over a period of weeks to ensure that the syntax will support future expansion. As a result, all previous |* lines are removed. This document serves as a new base-line. All of the existing syntax is retained with just a few additions noted below. BIRD75.7 reflects and related rules reflect a changed emphasis. With the exception of true differential circuits, [External Model] is intended to support native IBIS methodology, and [External Circuit] is allows more general future model support and support of the interconnect specification. List of some major changes: 1 - The presentation was reorganized, and the introductory material is significantly expanded. Several terms in the document are now defined. 2 - [External Model] used for "native" IBIS topologies only (except for retaining true differential circuit support). [Pin Mapping] instead of [Circuit Call] is used for [Model] connections with [External Model]. 3 - [External Circuit] expanded to support models, including recognizing predefined controls and signals D_drive, D_enable, D_receiver. 4 - A_to_D and D_to_A are restricted to SPICE only. 5 - corner_name is added to the above conversions to support Typ/Min/Max corners. 6- Language relating to supporting proprietary SPICE is removed. 7 - CIRCUITCALL signals an [External Circuit] connection to a pin. 8 - Required rules for C_comp* and [Ramp] were removed when [External Model] is used. BIRD75.7 and BIRD77.2 should be considered together. Pending BIRD78.1 and BIRD80 also support some related features. BIRD75.8 Minor editorial corrections and explaination clarifications. ****************************************************************************** ANY OTHER BACKGROUND INFORMATION: BIRD75 is follow up to an introductory given at the IBIS Summit Meetings on January 28, 2002 and March 8, 2002. BIRD77 is needed to document some new subparameters to existing IBIS keywords for [Model] and [Model Spec]. ******************************************************************************