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BIRD ID#:        77.2
ISSUE TITLE:     Differential Subparameter Additions
REQUESTER:       Bob Ross, Mentor Graphics
DATE SUBMITTED:  July 15, 2002, July 26, 2002, December 20, 2002
DATE ACCEPTED BY IBIS OPEN FORUM:  January 10, 2003

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STATEMENT OF THE ISSUE:

In considering the needed true differential buffer capability extention
for Multi-Lingual support in BIRD75, some new Model_type parameters 
under [Model] and some differential timing test load parameters under
[Model] and [Model Spec] are needed.

******************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

The [Model] keyword from the Draft Version 4.0 document is modified to 
cover differential buffers by adding four new model types and two new
timing subparameters.

|=============================================================================
|     Keyword:  [Model] 
|    Required:  Yes
| Description:  Used to define a model, and its attributes.
|  Sub-Params:  Model_type, Polarity, Enable, Vinl, Vinh, C_comp,
|               C_comp_pullup, C_comp_pulldown, C_comp_power_clamp,
|               C_comp_gnd_clamp, Vmeas, Cref, Rref, Vref
| Usage Rules:  Each model type must begin with the keyword [Model].  The
|               model name must match the one that is listed under a [Pin],
|               [Model Selector] or [Series Pin Mapping] keyword and must
|               not contain more than 20 characters.  A .ibs file must 
|               contain enough [Model] keywords to cover all of the model
|               names specified under the [Pin], [Model Selector] and [Series
|               Pin Mapping] keywords, except for those model names that use
|               reserved words (POWER, GND and NC).
|
|               Model_type must be one of the following:
|
|                 Input, Output, I/O, 3-state, Open_drain, I/O_open_drain,
|                 Open_sink, I/O_open_sink, Open_source, I/O_open_source,
|                 Input_ECL, Output_ECL, I/O_ECL, 3-state_ECL, Terminator,
|                 Series, and Series_switch.
|
|*              For true differential models documented under Section 6b,
|*              Model_type must be one of the following:
|*
|**               Input_diff, Output_diff, I/O_diff, and 3-state_diff
|*
|               Special usage rules apply to the following.  Some
|               definitions are included for clarification:
|
|               Input              These model types must have Vinl and Vinh
|               I/O                defined.  If they are not defined, the
|               I/O_open_drain     parser issues a warning and the default
|               I/O_open_sink      values of Vinl = 0.8 V and Vinh = 2.0 V
|               I/O_open_source    are assumed.
|
|               Input_ECL          These model types must have Vinl and Vinh
|               I/O_ECL            defined.  If they are not defined, the
|                                  parser issues a warning and the default
|                                  values of Vinl = -1.475 V and Vinh =
|                                  -1.165 V are assumed.
|
|               Terminator         This model type is an input-only model
|                                  that can have analog loading effects on the
|                                  circuit being simulated but has no digital
|                                  logic thresholds.  Examples of terminators
|                                  are: capacitors, termination diodes, and
|                                  pullup resistors.
|
|               Output             This model type indicates that an output
|                                  always sources and/or sinks current and
|                                  cannot be disabled.
|
|               3-state            This model type indicates that an output
|                                  can be disabled, i.e., put into a high
|                                  impedance state.
|
|               Open_sink          These model types indicate that the output
|               Open_drain         has an OPEN side (do not use the [Pullup]
|                                  keyword, or if it must be used, set I =
|                                  0 mA for all voltages specified) and the
|                                  output SINKS current.  Open_drain model
|                                  type is retained for backward
|                                  compatibility.
|
|               Open_source        This model type indicates that the output
|                                  has an OPEN side (do not use the [Pulldown]
|                                  keyword, or if it must be used, set I =
|                                  0 mA for all voltages specified) and the
|                                  output SOURCES current.
|
|               Input_ECL          These model types specify that the model
|               Output_ECL         represents an ECL type logic that follows
|               I/O_ECL            different conventions for the [Pulldown]
|               3-state_ECL        keyword.
|
|               Series             This model type is for series models that
|                                  can be described by [R Series], [L Series],
|                                  [Rl Series], [C Series], [Lc Series],
|                                  [Rc Series], [Series Current] and [Series
|                                  MOSFET] keywords.
|                                 
|               Series_switch      This model type is for series switch
|                                  models that can be described by [On],
|                                  [Off], [R Series], [L Series], [Rl Series],
|                                  [C Series], [Lc Series], [Rc Series],
|                                  [Series Current] and [Series MOSFET]
|                                  keywords.
|
|*              Input_diff         These model types specify that the model
|*              Output_diff        defines a true differential model available
|*              I/O_diff           directly through the [External Model]
|*              3-state_diff       keyword documented in Section 6b.
|*
|               The Model_type subparameter is required.
|
|               The C_comp subparameter is required only when C_comp_pullup,
|               C_comp_pulldown, C_comp_power_clamp, and C_comp_gnd_clamp are
|               not present.  If the C_comp subparameter is not present, at
|               least one of the C_comp_pullup, C_comp_pulldown,
|               C_comp_power_clamp, or C_comp_gnd_clamp subparameters is
|               required.  It is not illegal to include the C_comp 
|               subparameter together with one or more of the remaining
|               C_comp_* subparameters, but in that case the simulator will
|               have to make a decision whether to use C_comp or the
|               C_comp_pullup, C_comp_pulldown, C_comp_power_clamp, and
|               C_comp_gnd_clamp subparameters.  Under no circumstances should
|               the simulator use the value of C_comp simultaneously with the
|               values of the other C_comp_* subparameters.
|
|               C_comp_pullup, C_comp_pulldown, C_comp_power_clamp, and
|               C_comp_gnd_clamp are intended to represent the parasitic
|               capacitances of those structures who's I-V characteristics
|               are described by the [Pullup], [Pulldown], [POWER Clamp] and
|               [GND Clamp] I-V tables.  For this reason, the simulator
|               should generate a circuit netlist so that, if defined, each of
|               the C_comp_* capacitors are connected in parallel with their
|               corresponding I-V tables, whether or not the I-V table exists.
|               That is, the C_comp_* capacitors are positioned between the 
|               signal pad and the nodes defined by the [Pullup Reference],
|               [Pulldown Reference], [POWER Clamp Reference] and [GND Clamp
|               Reference] keywords, or the [Voltage Range] keyword and GND.
|
|               The C_comp and C_comp_* subparameters define die capacitance.
|               These values should not include the capacitance of the
|               package. C_comp and C_comp_* are allowed to use "NA" for the
|               min and max values only.
|
|**             The Polarity, Enable, Vinl, Vinh, Vmeas, Cref, Rref, and Vref
|*              subparameters are optional.
|*
|**             Also, optional Rref_diff and Cref_diff subparameters discussed
|**             further in Section 6b support the true differential buffer
|**             timing
|*              test loads.  They are used only when the [Diff Pin] keyword
|*              connects two models, and each buffer references the same
|*              model.  The Rref_diff and Cref_diff subparameters can be used
|*              with the Rref, Cref, and Vref subparameters for a combined
|*              differential and signal-ended timing test load.  Single-ended
|*              test loads are permitted for differential applications.
|*
|*              The Rref_diff and Cref_diff are recognized only when the
|*              [Diff Pin] keyword connects the models.  This applies for the
|*              true differential buffers in Section 6b and also for
|*              differential buffers using identical single-ended models.
|*
|**             The Polarity subparameter can be
|               defined as either Non-Inverting or Inverting, and the Enable
|               subparameter can be defined as either Active-High or
|               Active-Low.
|
|               The Cref and Rref subparameters correspond to the test load
|               that the semiconductor vendor uses when specifying the
|               propagation delay and/or output switching time of the model.
|               The Vmeas subparameter is the reference voltage level that the
|               semiconductor vendor uses for the model.  Include Cref, Rref,
|               Vref, and Vmeas information to facilitate board-level timing
|               simulation.  The assumed connections for Cref, Rref, and Vref
|               are shown in the following diagram:
|
|                            _________
|                           |         |
|                           |      |\ |            Rref
|                           |Driver| \|------o----/\/\/\----o Vref
|                           |      | /|      |
|                           |      |/ |     === Cref
|                           |_________|      |
|                                            |
|                                           GND
|
|**              A single-ended or true differential buffer can have Rref_diff
|**              and Cref_diff.:
|**
|**                          _________
|**                         |         |
|**                         |      |\ |                Rref
|**                         |Driver| \|--o---o---o----/\/\/\--o Vref
|**                         |      | /|  |   |   |
|**                         |      |/ |  |   |  === Cref
|**                         |_________|  /   |   |
|**                                      \   |  GND
|**                            Rref_diff /  === 
|**                          _________   \   | Cref_diff
|**                         |         |  |   | 
|**                         |      |\ |  |   |         Rref
|**                         |Driver| \|--o---o---o----/\/\/\--o Vref
|**                         |      | /|          |
|**                         |      |/ |         === Cref
|**                         |_________|          |
|**                                             GND
|**
|**                                             
| Other Notes:  A complete [Model] description normally contains the following
|               keywords:  [Voltage Range], [Pullup], [Pulldown], [GND Clamp],
|               [POWER Clamp], and [Ramp].  A Terminator model uses one or
|               more of the [Rgnd], [Rpower], [Rac], and [Cac] keywords.  
|               However, some models may have only a subset of these keywords.
|               For example, an input structure normally only needs the 
|               [Voltage Range], [GND Clamp], and possibly the [POWER Clamp]
|               keywords.  If one or more of [Rgnd], [Rpower], [Rac], and 
|               [Cac] keywords are used, then the Model_type must be 
|               Terminator.
|-----------------------------------------------------------------------------
| Signals       CLK1, CLK2,...         | Optional signal list, if desired
[Model]         Clockbuffer
Model_type      I/O
Polarity        Non-Inverting
Enable          Active-High
Vinl = 0.8V                            | Input logic "low" DC voltage, if any
Vinh = 2.0V                            | Input logic "high" DC voltage, if any
Vmeas = 1.5V              | Reference voltage for timing measurements
Cref = 50pF               | Timing specification test load capacitance value
Rref = 500                | Timing specification test load resistance value
Vref = 0                  | Timing specification test load voltage
| variable         typ             min             max
C_comp             7.0pF           5.0pF           9.0pF
|
C_comp_pullup      3.0pF           2.5pF           3.5pF | These four can be
C_comp_pulldown    2.0pF           1.5pF           2.5pF | used instead of
C_comp_power_clamp 1.0pF           0.5pF           1.5pF | C_comp
C_comp_gnd_clamp   1.0pF           0.5pF           1.5pF
|**
|** EXAMPLE ADDED BELOW
|
| For a single-ended or true differential buffer (in Section 6b)
|
[Model]         External_Model_Diff
Model_type      I/O_diff               | Requires [External Model]
Polarity        Non-Inverting
Enable          Active-High
| The [Diff Pin] vdiff value overrides the thresholds below
Vinl = 0.8V                            | Input logic "low" DC voltage, if any
Vinh = 2.0V                            | Input logic "high" DC voltage, if any
|                         | The true differential measurement point is at 
|                         | the crossover voltage
|                         | The Vmeas value is overridden
Vmeas = 1.5V              | Reference voltage for timing measurements
|                         | Single-ended timing test load is still permitted
Cref = 5pF                | Timing specification test load capacitance value
Rref = 500                | Timing specification test load resistance value
Vref = 0                  | Timing specification test load voltage
|                         | These new subparameters are permitted for
|                         | single-ended differential operation based on the
|                         | [Diff Pin] keyword
Rref_diff = 100           | Timing specification differential resistance value
Cref_diff = 5pF           | Timing specification differential capasitor value
|
|** END OF ADDED EXAMPLE
|=============================================================================
|     Keyword:  [Model Spec]
|    Required:  No
|  Sub-Params:  Vinh, Vinl, Vinh+, Vinh-, Vinl+, Vinl-, S_overshoot_high,
|               S_overshoot_low, D_overshoot_high, D_overshoot_low,
|               D_overshoot_time, Pulse_high, Pulse_low, Pulse_time, Vmeas,
|               Vref, Cref, Rref, Cref_rising, Cref_falling, Rref_rising,
|               Rref_falling, Vref_rising, Vref_falling, Vmeas_rising, 
|*              Vmeas_falling, Rref_diff, Cref_diff
| Description:  The [Model Spec] keyword defines four columns under which
|               specification subparameters are defined.  
|               
|               The following subparameters are defined:
|               Vinh               Input voltage threshold high
|               Vinl               Input voltage threshold low
|               Vinh+              Hysteresis threshold high max Vt+
|               Vinh-              Hysteresis threshold high min Vt+
|               Vinl+              Hysteresis threshold low max Vt-
|               Vinl-              Hysteresis threshold low min Vt-
|               S_overshoot_high   Static overshoot high voltage
|               S_overshoot_low    Static overshoot low voltage
|               D_overshoot_high   Dynamic overshoot high voltage
|               D_overshoot_low    Dynamic overshoot low voltage
|               D_overshoot_time   Dynamic overshoot time
|               Pulse_high         Pulse immunity high voltage
|               Pulse_low          Pulse immunity low voltage
|               Pulse_time         Pulse immunity time
|               Vmeas              Measurement voltage for timing measurements
|               Vref               Timing specification test load voltage
|               Cref               Timing specification capacitive load
|               Rref               Timing specification resistance load
|               Cref_rising        Timing specification capacitive load for
|                                  rising edges
|               Cref_falling       Timing specification capacitive load for
|                                  falling edges
|               Rref_rising        Timing specification resistance load for
|                                  rising edges
|               Rref_falling       Timing specification resistance load for
|                                  falling edges
|               Vref_rising        Timing specification test load voltage for
|                                  rising edges
|               Vref_falling       Timing specification test load voltage for
|                                  falling edges
|               Vmeas_rising       Measurement voltage for rising edge timing
|                                  measurements
|               Vmeas_falling      Measurement voltage for falling edge timing
|                                  measurements
|*              Rref_diff          Timing specification differential
|*                                 resistance load
|*              Cref_diff          Timing specification differential
|*                                 capacitive load
|
| Usage Rules:  [Model Spec] must follow all other subparameters under the 
|               [Model] keyword.
|
|               For each subparameter contained in the first column, the 
|               remaining three hold its typical, minimum and maximum values.
|               The entries of typical, minimum and maximum must be placed on
|               a single line and must be separated by at least one white
|               space.  All four columns are required under the [Model Spec]
|               keyword.  However, data is required only in the typical
|               column.  If minimum and/or maximum values are not available,
|               the reserved word "NA" must be used indicating the typical
|               value by default.
|
|               The minimum and maximum values are used for specifications
|               subparameter values that may track the min and max operation
|               conditions of the [Model].  Usually it is related to the
|               Voltage Range settings.
|
|               Unless noted below, no subparameter requires having present
|               any other subparameter.
|      
|               Vinh, Vinl rules:
| 
|               The threshold subparameter lines provide additional min and
|               max column values, if needed.  The typ column values are still
|               required and would be expected to override the Vinh and Vinl
|               subparameter values specified elsewhere.  Note: the syntax
|               rule that require inserting Vinh and Vinl under models remains
|               unchanged even if the values are defined under the [Model
|               Spec] keyword.
|
|               Vinh+, Vinh-, Vinl+, Vinl- rules:
|
|               The four hysteresis subparmeters (used for Schmitt trigger
|               inputs for defining two thresholds for the rising edges and
|               two thresholds for falling edges) must all be defined before
|               independent input thresholds for rising and falling edges of
|               the hysteresis threshold rules become effective.  Otherwise
|               the standard threshold subparameters remain in effect.  The
|               hysteresis thresholds shall be at the Vinh+ and Vinh- values
|               for a low-to-high transition, and at the Vinl+ and Vinl-
|               values for a high-to-low transition.
|
|         |
|         |           Receiver Voltage with Hysteresis Thresholds
|         |
|         |
|         |       Rising Edge                            Falling Edge
|         |    Switching Region   oo    o              Switching Region
|         |                  |  o    oo  ooooooooo           |
|         |                  V o                    o        |
|  Vinh+  - - - - - - - - - - x                        o     |
|  Vinh-  - - - - - - - - -  x                           o   |
|         |                 o                             o  |
|         |                o                               o |
|         |               o                                 oV
|  Vinl+  - - - - - - -  o - - - - - - - - - - - - - - - - - x
|  Vinl-  - - - - - - - o  - - - - - - - - - - - - - - - - -  x
|         |           o                                         o
|         |        o                                               o
|         |oooooo-----------------------------------------------------oooooooo
|
|                                       Time -->
|
|               S_overshoot_high, S_overshoot_low rules:
|
|               The static overshoot subparameters provide the DC voltage
|               values for which the model is no longer guaranteed to function
|               correctly.  Typically these are voltages that would cause the
|               physical component to be destroyed.
|
|               D_overshoot_high, D_overshoot_low, D_overshoot_time rules:
|
|               The dynamic overshoot values provide a time window during
|               which the overshoot may exceed the static overshoot limits
|               but be below the dynamic overshoot limits.  D_overshoot_time
|               is required for dynamic overshoot testing.  In addition, if
|               D_overshoot_high is specified, then S_overshoot_high is
|               necessary for testing beyond the static limit.  Similarly, if
|               D_overshoot_low is specified, then S_overshoot_low is
|               necessary for testing beyond the static limit.
|                
|         |
|         |     Receiver Voltage with Static and Dynamic Overshoot Limits
|         |
|         |
|         |   D_overshoot_time ->|      |<-
|         |                      |      |
|  D_overshoot_high - - - - - - -+ - - -+                       
|         |                      | oo   |  Passes - Does Not Exceed Bounds
|         |                      |o  o  |
|  S_overshoot_high - - - - - - -x    o +- - - - - - - - - - - - - - - - - - -
|         |                     o      o ooooooooo 
|         |                    o        o         o
|         |                   o                    o
|         |                  o                      o
|         |                 o                        o
|         |                o                          o
|         |               o                            o
|         |              o                              o        Fails -
|         |             o                                o    Exceeds Bounds
|         |           o                                   o      |   |  |
|         |        o                                       o     V   V  V
|         |oooooo-------------------------------------------o---------o---oooo
|  S_overshoot_low - - - - - - - - - - - - - - - - - - - - - x      +x x x - -
|         |                                                  |o     x   x
|         |                                                  | o   o|
|  D_overshoot_low - - - - - - - - - - - - - - - - - - - - - + -x x-+
|         |                                                  |   x  |
|                                         D_overshoot_time ->|      |<-
|
|                                       Time -->
|
|               Pulse_high, Pulse_low, Pulse_time rules:
|
|               The pulse immunity values provide a time window during which
|               a rising pulse may exceed the nearest threshold value but
|               be below the pulse voltage value and still not cause the
|               input to switch.  Pulse_time is required for pulse immunity
|               testing.  A rising response is tested only if Pulse_high is
|               specified.  Similarly, a falling response is tested only if
|               Pulse_low is specified.  The rising response may exceed the
|               Vinl value, but remain below the Pulse_high value.
|
|               Similarly, the falling response may drop below the Vinh value,
|               but remain above the Pulse_low value.  In either case the
|               input is regarded as immune to switching if the responses
|               are within these extended windows.  If the hysteresis
|               thresholds are defined, then the rising response shall use
|               Vinh- as the reference voltage, and the falling response shall
|               use Vinl+ as the reference voltage.
|
|         |
|         |         Receiver Voltage with Pulse Immunity Thresholds
|         |
|         |
|         |            Switching                           No Switching
|         |                |                               |
|         |                |      oo    o                  |  Switching
|         |                |    o    oo  ooooooooo         |      |
|         |                |   o                    o      |      | 
|         |                V  o                       o    V   oooV
|  Vinh - - - - - - - - - -  x - - - - - - - - - - - - - x   o + -x
|         | Pulse_time ->|  o  |<-                       |ooo  |   o
|  Pulse_high - - - - -  + o - +            Pulse_low  - + - - +    o   
|         |              |o    |            Pulse_time ->|     |<-   o       
|  Vinl - - - - - - - -  x     + - - - - - - - - - - - - - - - - - -  x
|         |             o                                              o
|         |           o                                                 o
|         |        o                                                      o
|         |oooooo------------------------------------------------------------o
|
|                                       Time -->
|
|               Vmeas, Vref, Cref, Rref rules:
|  
|               The Vmeas, Vref, Cref and Rref values under the [Model Spec]
|               keyword override their respective values entered elsewhere.
|               Note that a Vmeas, Vref, Cref or Rref subparameters may not be
|               used if its edge specific version (*_rising or *_falling) is
|               used.
|  
|               Cref_rising, Cref_falling, Rref_rising, Rref_falling,
|               Vref_rising, Vref_falling, Vmeas_rising, Vmeas_falling rules:
|  
|               Use these subparameters when specifying separate timing test
|               loads and voltages for rising and falling edges.  If one
|               'rising' or 'falling' subparameter is used, then the
|               corresponding 'rising' or 'falling' subparameter must be
|               present.  The values listed in these subparameters override 
|               any corresponding Cref, Vref, Rref or Vmeas values entered
|               elsewhere.
|*
|*              Rref_diff, Cref_diff rules:
|*
|*              The Rref_diff and Creff_diff values under the [Model Spec]
|*              keyword override their respective values entered elsewhere.
|*              These subparameters are used only when the model is referenced
|*              by the [Diff Pin] keyword.  These follow the same rules as
|*              the corresponding subparameters documented under the [Model]
|*              keyword.  See Section 6b for more discussion on true and
|*              single-ended differential operation.
|-----------------------------------------------------------------------------
[Model Spec]
|   Subparameter          typ        min        max
|
| Thresholds
|
Vinh                      3.5        3.15       3.85    | 70% of Vcc
Vinl                      1.5        1.35       1.65    | 30% of Vcc
|
| Vinh                    3.835       3.335     4.335   | Offset from Vcc
| Vinl                    3.525       3.025     4.025   | for PECL
|
| Hysteresis
|
Vinh+                     2.0        NA         NA      | Overrides the
Vinh-                     1.6        NA         NA      | thresholds
Vinl+                     1.1        NA         NA 
Vinl-                     0.6        NA         NA      | All 4 are required
|
| Overshoot
|
S_overshoot_high          5.5        5.0        6.0     | Static overshoot
S_overshoot_low          -0.5        NA         NA
D_overshoot_high          6.0        5.5        6.5     | Dynamic overshoot
D_overshoot_low          -1.0       -1.0       -1.0     | requires
|                                                       | D_overshoot_time 
D_overshoot_time          20n        20n        20n     | & static overshoot
|
| Pulse Immunity
|
Pulse_high                3V         NA         NA      | Pulse immunity
Pulse_low                 0          NA         NA      | requires
Pulse_time                3n         NA         NA      | Pulse_time
|
| Timing Thresholds
|
Vmeas                     3.68       3.18       4.68    | A 5 volt PECL
|                                                       | example
|
| Timing test load voltage reference example
|
Vref                      1.25       1.15       1.35    | An SSTL-2 example
|
|
| Rising and falling timing test load example (values from PCI-X
| specification)
|
Cref_falling              10p        10p         10p
Cref_rising               10p        10p         10p
Rref_rising               25         500         25  | typ value not specified
Rref_falling              25         500         25  | typ value not specified
Vref_rising               0          1.5         0     
Vref_falling              3.3        1.5         3.6   
Vmeas_rising              0.941      0.885       1.026 | vmeas = 0.285(vcc)
Vmeas_falling             2.0295     1.845       2.214 | vmeas = 0.615(vcc)
|   
|** EXAMPLE ADDITIONS BELOW
|
| Differential timing test load for true or single-ended differential model
| 
Rref_diff                 100        90         110
Cref_diff                 5pF        NA         NA
|
|** END OF EXAMPLE ADDITIONS
|=============================================================================


******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

The new Model_type subparameters Input_diff, Output_diff, I/O_diff and
3-state_diff are the best way to identify [External Model] references for
true differential buffers.  An indirect method based on identifying
the reserve A_signal_pos and A_signal_neg signal names is possible, but
this would require searching within the [Model] section.

Differential buffers, whether based on the true differential model 
capability of [External Model] or based on single-ended buffer construction
need a set of differential timing loads.  This proposal generalizes the
timing load with Rref_diff and Cref_diff subparameters with the following
rules:

  1.  They are used only when identical models are connected using the
      [Diff Pin] keyword
  2.  The subparameters are optional in all cases, and they also can be
      used with the existing Rref, Cref and Vref subparameters for a
      combined differential and single-ended test load
  3.  They are entered both under the [Model] and [Model Spec] keyword.

The proposal is to document the Rref_diff and Cref_diff subparmeters
completely in a manner consistent with the other timing subparameters.
An alternative would have been to just use the [Model Spec] keyword only.

These changes are shown by |* lines

BIRD77.1 adds some examples and a diagram of the differential timing
reference loads.  It also has some editorial changes.  Changes are shown
by |** lines

BIRD77.2 corrects the Model_type to I/O_diff.  This change is not shown.

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ANY OTHER BACKGROUND INFORMATION:

BIRD77 should be considered with BIRD75.2.  Applications are introduced
under Section 6b.

Note, the baseline descriptions of [Model] and [Model Spec] are based on
anticipated IBIS Version 4.0 processing and may change as a result of
actual IBIS Verison 4.0 processing.

BIRD77.1 captures the changes.

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