****************************************************************************** ********************* IBIS GOLDEN PARSER BUG REPORT FORM ********************* ****************************************************************************** INSTRUCTIONS To report a bug in the IBIS golden parser. Please fill out the top part of the following form and send the complete form to ibis-bug@ibis.org. A list of reported bugs will be maintained on ibis.org. ****************************************************************************** PARSER VERSION NUMBER: IBISCHK6 V6.1.2 PLATFORM (SPARC, HP700, PC, etc.): PC OS AND VERSION: Windows 7 REPORTED BY: Arpad Muranyi, Mentor Graphics; and Bob Ross, Teraspeed Labs DATE: May 26, 2016 DESCRIPTION OF BUG: For Multi-lingual [External Model], Error not issued for extra undeclared port. Even though Node out3 is declared in the Ports list and exists in the SPICE model, it is not declared in a D_to_A (or a A_to_D line for I/O* and Output* buffers. An Error message such as "[External Model] %s port %s is not a reserved port name and is not used as a D_to_A or _A_to_D port" should be issued. ----- INSERT IBIS FILE DEMONSTRATING THE BUG: bug176.ibs ---------- |**************************************************************** [IBIS Ver] 4.2 [Disclaimer] This model is for testing the IBIS parser only. [File Name] bug176.ibs [File Rev] 0.0 [Date] May 24, 2016 [Source] Developed by Arpad Muranyi [Component] BUG176 [Manufacturer] None | [Package] | R_pkg 0.0 0.0 0.0 L_pkg 0.0 0.0 0.0 C_pkg 0.0 0.0 0.0 | [Pin] signal_name model_name R_pin L_pin C_pin 1p8V Vcc1p8 POWER 0p0V GND0p0 GND | Q0p DQS_p Rx NA NA NA Q0n DQS_n Rx NA NA NA | [Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max Q0p Q0n 0.1V NA NA NA | |**************************************************************** | [Model] Rx Model_type Input_diff | | typ min max C_comp 0.0pF 0.00pF 0.00pF [Voltage Range] 1.8V 1.71V 1.89V [Temperature Range] 25C 100C 0.0C | [External Model] Language SPICE | | Corner corner_name file_name circuit_name (.subckt name) Corner Typ bug176.sp BUG176 | | Ports List of port names (in same order as in SPICE) Ports A_signal_pos A_signal_neg Ports out1 out2 Ports out3 | No Error for extra Port Ports A_pcref A_gcref | | A_to_D d_port port1 port2 vlow vhigh corner_name A_to_D D_receive out1 out2 -0.01 0.01 Typ | [End External Model] | |**************************************************************** [END] bug176.sp --------- ************************************************************************* .subckt BUG176 in1 in2 out1 out2 out3 vcc vss R1 in1 in2 R=100 R2 out1 out2 R=100 .ends ****************************************************************************** ******************** BELOW FOR ADMINISTRATION AND TRACKING ******************* ****************************************************************************** BUG NUMBER: 176 SEVERITY: [FATAL, SEVERE, MODERATE, ANNOYING, ENHANCEMENT] MODERATE PRIORITY: [HIGH, MEDIUM, LOW] MEDIUM STATUS: [OPEN, CLOSED, WILL NOT FIX, NOT A BUG] CLOSED FIXED VERSION: 6.1.3 FIXED DATE: December 2, 2016 NOTES ON BUG FIX: Classified at the June 10, 2016 IBIS Teleconference Meeting. To be fixed in the next release of ibischk6. ****************************************************************************** ******************************************************************************