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IBIS EDITORIAL TASK GROUP
http://www.ibis.org/editorial_wip/ 
Mailing list: ibis-editorial@freelists.org 
Archives at http://www.freelists.org/archive/ibis-editorial/ 
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Attendees from April 1 Meeting (* means attended at least using audio)
ANSYS                              Curtis Clark*
Cadence Design Systems             Bradley Brim
Cisco                              David Siadat
Intel Corp.                        Michael Mirmak*
Keysight Technologies              Radek Biernacki*
Mentor Graphics                    Arpad Muranyi*
Micron Technology                  Justin Butterfield, Randy Wolff*
SAE ITC                            Maureen Lemankiewicz, Logen Johnson
Signal Integrity Software          Walter Katz*, Mike LaBonte*
Teraspeed Labs                     Bob Ross*
University of Aveiro in Portugal   Wael Dghais

Michael Mirmak convened the meeting.  No patents were declared.   

Arpad Muranyi moved to approve the minutes of the March 25 meeting.  
Walter Katz seconded.  No objections were raised and the minutes were 
approved.


During opens Bob Ross mentioned that he has roughed out a presentation 
on various names of terminals and places to be careful in the document.  

Mike LaBonte presented his “IBIS 6.2 Editorial Resolutions”, which 
resulted from scouring through minutes to get information about 
proposed changes.   He suggested producing a single BIRD to include a 
document that will become IBIS 6.2, but there could be other BIRDs on 
specific topics.

Mike noted that he has added a new definitions section, but the 
document may not need it.  Walter suggested that the word “Port” should 
be added. Michael suggested “Rail”.  Radek Biernacki suggested 
“Reference”.  Arpad notes that reserved words belong under [Pin], not 
[Model].  Mike corrected this.

The remainder of the document consists of 17 pages, each on a separate 
topic, described below.  All pages refer to the posted PDF version of 
IBIS 6.1. 

C_comp: Radek suggests that the C_comp section requires more global 
modification, not just the last sentence.  

Vih/Vil: Walter noted that, if we say that IBIS only describes DUT 
(device-under-test), then the Vinh & Vinl reference node is clear.  
If we define DIA (device-in-action) in a separate section, then 
referencing for these is required.  Radek added that Vinl and Vinh may 
not be defined correctly for ECL/PECL.

Figures 1 & 2: Walter suggested the SPICE2IBIS assumptions define a 
virtual test fixture.  The reference node in Figures 1 & 2 are DUT-
related.  Radek noted that buffer reference terminals are not shown in 
the figures; Mike, replied that they are present and are “dangling”.

[Voltage Range], [* Reference]: Michael stated that he is “horrified” 
by the ongoing confusion between rail and voltage value concepts in 
the text for these keywords.  These will require significant rewriting 
to clarify.

I-V Table reference connections: Bob noted that ECL could be 
referenced to a GND pin.  Radek replied that these are using two 
different concepts – you can define how the I-V tables are referenced, 
completely irrespective of whether you have [Pin Mapping] or not.  
There is a distinction between [Pin Mapping]-like connection to rails 
and actual pins.  

Figures 7-10: Walter suggested the phrase “Vcc or pullup reference” 
should be labeled as [Pullup Reference].

Figure 11: Radek suggested this should be clarified to apply to either 
DUT or DIA (or both).

Figure 16: Bob noted that this figure shows where composite current 
flows.  Note that [Voltage Range] is involved.  Mike replied that 
“absolute GND” is used here.

Figure 17: Walter noted that this is the fixture for measuring 
[Composite Current].  Bob agreed, except with removal of the package 
elements.  Randy Wolff added that ESR, ESL, pre-driver are more 
informational; they are present and assumed, but not really modeled in 
IBIS.  Walter stated that this can be done with SPICE implementations.

Table 12: Walter mentioned differences between Verilog and Berkeley 
SPICE.  “Port” is language used by Verilog for what we call “terminals” 
or “nodes”.  Radek disagrees with the referencing interpretation used 
in this section.  

Figure 29: GND used as a signal name.  Walter suggested this could be 
bus label.  Bob replied that there’s an exclusion for application of 
bus labels to [External Circuit].  Radek asked whether Mike has looked 
at Walter’s presentation where the necessary changes are made.  Walter 
noted that he has worked with Mike already on this section.  

For next time, the team will review Bob’s presentation and Walter’s 
proposal for distinguishing between DUT and DIA.  The team will also 
review Mike’s second presentation and new drawings.    

Mike moved to adjourn.  Radek seconded the motion.  The meeting 
adjourned.