====================================================================== IBIS EDITORIAL TASK GROUP http://www.ibis.org/editorial_wip/ Mailing list: ibis-editorial@freelists.org Archives at http://www.freelists.org/archive/ibis-editorial/ ====================================================================== Attendees from April 1 Meeting (* means attended at least using audio) ANSYS Curtis Clark* Cadence Design Systems Bradley Brim Cisco David Siadat Intel Corp. Michael Mirmak* Keysight Technologies Radek Biernacki* Mentor Graphics Arpad Muranyi* Micron Technology Justin Butterfield, Randy Wolff SAE ITC Maureen Lemankiewicz, Logen Johnson Signal Integrity Software Walter Katz*, Mike LaBonte* Teraspeed Labs Bob Ross* University of Aveiro in Portugal Wael Dghais Michael Mirmak convened the meeting. No patents were declared. Radek Biernacki moved to approve the minutes of the April 1 meeting. Arpad Muranyi seconded. No objections were raised and the minutes were approved. During opens, Bob Ross mentioned that he has roughed out a presentation on various names of terminals and places in the document to be careful. Mike LaBonte observed that his presentation, mentioned in the last meeting but not reviewed, has already been shown elsewhere and does not now require review. Mike added that he has updated three slides of the task list reviewed at the last meeting. On DUT and DIA, Walter Katz asked whether there was general agreement that DUT and not DIA is described by IBIS today. He mentioned that Curtis Clark had found that the ISSO keywords mention the DUT vs. DIA distinction, but no other keywords do. Because industry experts Walter consulted “go catatonic” at the mention of “ground” or “GND”, Walter’s proposed that, for every I/O pin, we need to know what it’s return path node is, or more precisely the “return path terminal” of the buffer model. Radek replied that we are talking about a port, which consists of two terminals. Arpad added that we need to distinguish talking about voltages vs. circuits. Voltages require references, while circuits describe paths. The question is whether ground terminals are parts of voltage reference paths or current return paths. Radek replied that they are both, very clearly. Walter stated that every buffer has three terminals – what you connect voltage to, one to which you connect ground, one which you use for I/O. All voltages are supplied or connected by the simulator. Michael asked whether the “reference” is a terminal or the circuit return path. Radek replied that it is both. I/O terminals have voltage reference terminals. Both must be mentioned or described. Arpad stated that he thought the discussion was exclusive to a voltage reference terminal; this always exists for each rail. For the 5 volt rail, what is the “return path”? This is a reference point. Walter noted that we are always talking about differences in voltages. Arpad responded that the question is what reference is used for the [* Reference] keywords. Michael asked whether Walter’s presentation/proposal covers this as a single node, and we are just trying to describe this fact. Walter replied that everything is simple when one of the nodes of the buffer is also the reference of the test fixture. We know what to do when we run models in DUT conditions; in non-DUT conditions (DIA) we do not know what to do. Radek suggested this is only partially true. What IBIS gives is an IP-protected model framework, and we want to provide model data to allow the model to be simulate-able in an EDA tool. Data provided today may be static, which should be good for certain conditions. The circuit can be a black box. For the I-V terminals, we have to decide how to define them. For those terminals, we have to capture voltage relationships between the them. The “potential at a point” is not meaningful. Our question is what to do with non-zero ground clamp reference. We therefore need to identify second reference terminal for keywords, Michael suggested that all that is needed is a leading paragraph, leaving aside the ISSO, Pin Mapping, and Composite Current keywords, to describe the DUT assumption. He accepted the AR to write this paragraph. Walter summarized SiSoft’s perspective: they have only seen models where [GND Clamp Reference] and [Pulldown Reference] are both zero- valued. [Pullup Reference] and [POWER Clamp Reference] differences are seen occasionally. Walter thinks a second document on how to use these models in a simulator might be useful. Bob stated that he does not agree with all these conclusions/statements made so far; each of the [* Reference] keywords can be clearly described with respect to some reference; in the DUT terminology, that’s a test fixture reference. We simply move the voltages as part of the IBIS model structure, and this relates to reference voltages and other IBIS content, such as I-V and fixture voltages. V-t tables are extracted as if with respect to an external reference. Additionally, the B-element usually involves power-on and power-off states. In power-on state, the buffer uses the model-documented voltages with assumed DC supplies. How are the voltages generated, and are they with respect to node zero? Michael suggested the fixture voltages are measured with respect to an as-yet-unnamed terminal. Bob agreed. Arpad replied that the buffer thresholds are stated with respect to the buffer pin reference. Bob disagree, citing the IBIS specification on p. 41, showing a PECL example. Michael asked whether saying the reference terminal is now known actually result in radical changes in tool and possibly buffer model assumed behavior? Bob agreed, adding that we don’t want drastically different answers between simulators if DUT vs. DIA is the cause. Next time, the proposed paragraph will be reviewed. Mike moved to adjourn. Arpad seconded the motion. The meeting adjourned.