(attaching a text version of the minutes for ease of archiving) ====================================================================== IBIS EDITORIAL TASK GROUP http://www.ibis.org/editorial_wip/ Mailing list: ibis-editorial@freelists.org Archives at http://www.freelists.org/archive/ibis-editorial/ ====================================================================== Attendees from April 22 Meeting (* means attended at least using audio) ANSYS Curtis Clark Cadence Design Systems Bradley Brim Cisco David Siadat Intel Corp. Michael Mirmak* Keysight Technologies Radek Biernacki* Mentor Graphics Arpad Muranyi* Micron Technology Justin Butterfield, Randy Wolff* SAE ITC Maureen Lemankiewicz, Logen Johnson Signal Integrity Software Walter Katz, Mike LaBonte* Teraspeed Labs Bob Ross* University of Aveiro in Portugal Wael Dghais Michael Mirmak convened the meeting. No patents were declared. Walter Katz could not attend. Arpad Muranyi moved to approve the minutes of the April 15 meeting. Bob Ross seconded. No objections were raised and the minutes were approved. The agenda was ordered to cover first Bob’s presentation, then Michael’s suggested reference paragraphs for the opening portion of the specification. Bob’s presentation focused on IBIS partitioning. Much of IBIS is informational, and model extraction and usage are different. Michael asked whether this is therefore an assumption that is implied but should be understood as the IBIS context. Bob answered yes. For the IBIS reference, no pins or packages are involved. All rails are with respect to an external reference, which could be (an ideal) ground from a SPICE simulator perspective. That’s the way models are extracted today. Radek Biernacki reiterated statements he made at the Interconnect meeting earlier in the week. He suggested that we are mixing up the concepts of 0 V and node zero; this will be clarified later. Bob referred to Mike LaBonte’s solution diagram for C_comp and breaking up C_comp. He also noted that Composite Current tables include data to show synchronization between the I/O, power rail and Vss rail. Bob suggested the proposed paragraphs for the specification be changed to mention voltages with respect to ideal node zero for SPICE, and use the language, “unless otherwise noted”. Radek suggested that node zero is the reference used for all voltages, as selected by the simulator. For IBIS, we can select a reference that may not necessarily be this node zero; the [* Reference] keyword values are with respect to this node. 0.0 V does not necessarily mean a connection to ideal node zero. There is a distinction between GND and ideal node zero within IBIS. Mike noted that voltages produced or measured require two terminals. Bob replied that a local reference/external reference might be correct. PECL/ECL and RS-232 use unusual referencing. Mike asked if these unusual situations should be addressed by new diagrams. Michael observed that the most common SPICE implementation does not distinguish between “GND”, “GROUND” and node 0. Mike stated that he would like to make a distinction between GND and ideal 0. He suggested adding language regarding the simulator choosing rail voltages. Radek recommended caution; there will be differences always, but the topology and connections should be consistent across tools. Mike replied that therefore there’s no doubt about the model operation if it is operated as it was tested (as the data was extracted). This would mean adding a listing of [Submodel], etc. keywords that refer to DIA (which would be the “simulation model” in Radek’s preferred language). Bob suggested removing the statement referring to what IBIS files do not define; this can be added to Chapter 6. In a third paragraph, we can reinforce the DIA/DUT distinction. Mike moved to adjourn. Radek seconded the motion. The meeting adjourned.