RE: standard loads on 66 MHz PCI

Greg,
        As you may know, one of the ways we handle this (in our internal
simulator) is it by having a unique standard load entry for each corner
and for each rise/fall transistion. This way you do not need to make
multiple runs in order to obtain corner analysis for different standard
loads. I wonder if this idea could be extended for IBIS ? just my $.02
regards,
Bob Haller

        ----------
        From: Gregory R Edlund[SMTP:gedlund@us.ibm.com]
        Sent: Tuesday, November 10, 1998 11:35 AM
        To: ibis-users@vhdl.org
        Subject: Re: standard loads on 66 MHz PCI

        Is it a requirement to demonstrate compliance with the PCI Tval
spec on the
        component datasheet? I'm already taking PCI compliance on faith
because most
        vendors do not include IV curves or rise/fall times on their
datasheets. In
        the case of PCI drivers, my main interest as a system designer
in the
        clock-to-out spec is as an input to my static timing analyzer.

        I agree with you that if vendors are specifying clock-to-out
delays using the
        PCI loads ONLY, then IBIS should be ammended to facilitate
seamless timing
        analysis. However, my preference would be that vendors use a
simple,
        traditional standard load. Simplicity reduces the probability
of random
        errors! Corner analysis using a single standard load has always
been possible
        - as long as the vendor specifies min/typ/max clock-to-out
delays.

        Greg Edlund
        Advisory Engineer, AS/400 System Timing
        IBM
        3650 Hwy. 52 N, Dept. HDC
        Rochester, MN 55901
        gedlund@us.ibm.com

        schumach@valencia.rsn.hp.com on 11/10/98 10:10:01 AM
        Please respond to schumach@valencia.rsn.hp.com
        To: Gregory R Edlund/Rochester/IBM@IBMUS
        cc: schumach@valencia.rsn.hp.com, ibis-users@vhdl.org
        Subject: Re: standard loads on 66 MHz PCI

> I wonder if this is really a non-issue? Does the somewhat
"unusual" passage
        in
> the PCI spec about Tval loading necessarily mean that the
vendor datasheet for
> that component must use the same loads? Couldn't the vendor
specify a
> "traditional" standard load in the datasheet and still comply
with PCI?

        How do you demonstrate compliance in all corner cases with a
        single load datasheet? Especially if that single load is not
        _any_ of those given in the design spec? Any device which
        complies in one corner case may comply in the others, or it
        may not. PCI takes the right approach in explicitly specifying
        the corner cases. It's up to customers to demand appropriate
        data sheets and models.

        Is it feasible to expand the IBIS model spec and build enough
        intelligence into the simulators so that together they can
        automatically simulate all the corner cases in a given design?
        That would be required to meet the logic designers' expectation
        for a plug-and-chug solution. (Most SPICEs have monte carlo
        capabilities for such work; they require manual intervention
        to set parameter limits et cetera, but at least they don't
        require a different model for each loading case. With a model
        consisting of multiple sets of I-V and V-T curves, one per
        loading case, there's more scope for error: knowing that the
        set for one case is correct does not tell the user whether the
        other sets are correct.)
Received on Tue Nov 10 09:03:37 1998