RE: timing on GTL+ bus

Wis,

This is covered in IBIS 3.x with the vinl and vinh under [Model Spec].
There you can specify typ, min, max for these thresholds.

Regards,
Weston Beal
Signal Integrity Engineer
Compaq Computer Corp.

                -----Original Message-----
                From: wis_macomson@mentorg.com
[mailto:wis_macomson@mentorg.com]
                Sent: Tuesday, 15 June, 1999 1:52 AM
                To: ibis-users@eda.org
                Subject: timing on GTL+ bus

                To All:

                Be aware that when simulating a GTL+ bus using some
processor
                models, you must adjust the receiver input thresholds when
the
                driver has different slow and fast models and assumes
different
                termination voltages in them.

                Some new processors have internal pull-up resistors for the
GTL bus,
                which reduces parts significantly, and result in extremely
                attractive signal quality when the processor receives. The
                resistors are connected to separate termination voltage
(Vtt) supply
                pins.

                When simulating slow corner for timing, one uses the low
termination
                voltage and high internal resistor values. The fast corner
uses
                high Vtt and low resistance. For the components with
internal pull-
                ups, this can be done with a model whose [Voltage Range] is
set to
                the termination voltage desired, and the V-I curves take
care of the
                resistor values.

                Remember that Vinl and Vinh for the GTL bus are based on
some
                reference voltage, Vref, which is typically developed via a
                resistive divider between Vtt and ground. For a widely used
GTL
                variant called "GTL+", Vtt = +1.5V and Vref is nominally
2/3*Vtt =
                +1.00V. Often, Vinl and Vinh are specified as offsets from
Vref,
                such as:

                        Vinl(max) = Vref - 200mV
                        Vinh(min) = Vref + 200mV

                In the nominal case listed above, then, Vinl would be
+0.800V, and
                Vinh would be +1.200V. Indeed, a popular GTL+ bridge
component has
                these values listed in its IBIS model.

                However, if Vtt is at its low margin level, for example
+1.35V, then
                Vref will be +0.900V, and the receiver thresholds should
"reflect"
                this. Using the example, Vinl(max) = +0.700V, Vinh(min) =
+1.100V.

                In the case where a slow corner model includes the low Vtt
value,
                the output voltage step may not be able to incident wave
switch
                on the low to high transition, if one uses the Vinh value
derived
                from the nominal Vtt as the timing point on the receiver
waveform.

                In a specific instance, the existing model for a GTL+ bridge
                component, with Vinl=+0.8V, Vinh=+1.2V, showed timing
violations on
                the slow corner. The slow corner drivers on the processor
showed a
                shelf just below +1.2V, when the PCB trace impedance was at
its low
                value. The voltage didn't cross the high threshold until
after the
                slow RC charging from the step up to Vtt, which violated
timing.

                Because Vtt and Vref were common to the processor and
bridge, it is
                reasonable to assume that the switching threshold at the
bridge
                would track the Vtt. Setting Vinh to +1.1V showed that the
timing
                was acceptable. (One just might think that they designed
the
                processor output buffers just big enough to handle the low
trace
                impedance case.)

                This discussion extends to the fast corner, where the
nominal
                thresholds would give an overly conservative (smaller) hold
time
                estimate, because the thresholds would be lower than actual.

                The unfortuate part of this is that you now need "slow" and
"fast"
                receiver models, as there is no "typ/min/max" for Vinl and
Vinh.

                The other point to keep in mind is that you need to be very
careful
                if you have a system design with separate Vtt supplies to
the loads
                on a GTL bus, or if you have separate Vref's to those loads.

                        Note: for margin, one could take into account the
                        tolerance of the divider resistors, and adust Vinl
                        and Vinh up or down appropriately.

                Regards,

                -wis
                --
                Wis Macomson
                SiQual
                c/o Wis_Macomson@mentor.com
Received on Tue Jun 15 20:22:16 1999