RE: Overclocked driver schedule.

Al,

This is what the spec says:

| Rise_on_dly is the amount of time that elapses from the
| internal simulator pulse initiating a RISING edge to the
| t=0 time of the waveform or ramp that turns the I-V table of
| the PULLUP device ON, and the t=0 time of the waveform or
| ramp that turns the I-V table of the PULLDOWN device OFF (if
| they were not already turned ON and OFF, respectively, by
| another event).

So, if the rise on delay is 3.5ns, and the logic high pulse is less that in
duration, that means that the t0 time for this scheduled pullup device never
happened. So it should not even begin to turn on. The pulldown that was
holding the signal low prior to this rising edge is turned off earlier by
the rising edge when the signal level goes above Vinl.

Therefore the answer is NO to both 1) and 2).

I hope this clarifies what to do.

Arpad Muranyi
Intel Corporation
==========================================================================

-----Original Message-----
From: Al Davis [mailto:aldavis@ieee.org]
Sent: Friday, August 11, 2000 12:07 AM
To: ibis-users@eda.org; ibis@eda.org
Subject: Overclocked driver schedule.

What is the correct behavior for a simulator when driver
schedule is overclocked?

Consider this ....

[Driver Schedule]
foo 3.5ps 5ns NA NA

.. this gives it an extra kick on a rising edge.

The question ...

What should happen when the device is triggered to fall 3ns
after the rise begins?

Some possibilities .....

1. It waits another 2 ns (for the total of 5 ns) to turn
off?

2. It turns off on the falling edge? as if the line was:
foo 3.5ps 5ns 0ns NA

3. Other?

Should the standard be changed to clarify this?
Received on Thu Aug 17 13:02:44 2000