Re: ibis VT curves

Katja,

Regarding non-standard dV/dt, the suspected cause of not following the IBIS
standard plays into how I handle
the situation. My simulation needs, however, are the major determinant of how I
respond.

I suspect two possible causes of non-standard, i.e. non 20%-80% intervals.

1. Carelessness and/or ignorance of what the standard calls for. My guess is
this is 20% of the cases.

2. Deliberately limiting the range to less than 20%-80% of full swing centered
around the 50% point. This
is because this is usually the most linear portion of the curve. There is a
mistaken belief out there that fast
switching speed is invariably good. Inclusion of the full 20%-80% swing usually
picks up soft corners
(non-linearity) resulting in a slower switching speed.

Since I'm a signal integrity engineer I usually am interested in the slowest
part that can switch in the required time.
Speed kills. Especially with today's die-shrunk sub-micron parts. I've yet to
run into a single instance of a part not
fast enough for its application by the time the logic designer has made their
choice an asked me to look into the SI
issues.

We all know our SI problems increase as circuit and topology becomes more
complex and speed, especially edge
rate, increases. Therefore, when I get a model with a dV/dt reduced from 20%-80%
to something less, I suspect it is
worthless for simulation in the faster, more complex cases. Especially, if I
suspect the range was reduced as part of
making the device more marketable in the eyes of a technically ignorant
supplier. The full 20%-80% range has, thus
far, always made the the simulation look better.

This, and the logic designer's need for an accurate, believable simulation and a
recommendation from me that his
circuit is just fine determines my level of motivation to pressure the supplier
for a corrected model.

Best Regards,

Roy

 
Received on Mon Nov 27 06:53:33 2000