RE: new ibischk3 V3.2.6

> Perhaps I should phrased my request differently to ask for other COMMON
> causes including ideal models. I'm not interested in what would happen if
> the models used **Superconductors** for traces.....
 
Hey, don't ALL models use superconductors for traces? :-) The normal
connection in a simulator is a zero resistance, zero delay "wire". Even the
old standard SPICE transmission line, has delay but no loss, i.e., a
superconductor.

Perhaps like Todd, I got confused when you said "realistic scenario". I
thought you meant what in the REAL world might give you giga-amps.

Nothing on an IC or a PC board will give you those kinds of currents. If
you see that much current in a simulation, you can say with 100% certainty
that the simulation, or the model, is wrong.

Some possible causes of such currents in a simulation:

(1) Ideal models where something, such as Rs, was left out. I believe the
parasitic diodes in many MOS models do not even provide for an Rs, so you
must add discrete resistor elements to fully represent the transistor.

(2) Models where the wrong units were used. For example, tables of Pullup,
Pulldown currents in microamps rather than amps.

(3) Improper use (or any use!?) of SCALE or SCALM in Hspice. Using models
that require different SCALE/SCALM parameters in the same simulation.
(BOYCOTT SCALE & SCALM!)

(4) Anything that causes the simulator to become unstable, usually showing
big oscillations when none should exist.

(5) Extrapolating a table beyong its endpoints without thinking. (Isn't
that why IBIS requires complete tables to unreasonable overshoot voltages so
the simulator doesn't have to extrapolate?)

(6) Anything that causes a model to be used beyond its intended and/or
tested and verified range.

(7) Improper use of global nodes, which can result in "sneak path" or "back
door" connections with no or very little resistance.

(8) Any number of model usage mistakes, typos, sloppy editing, etc.

Regards,
Andy

 
Received on Thu Jan 11 09:40:31 2001