RE: How to determine per length RLC in a board

SSO return paths and non-TEM effect have been compensated for in the Intel
Pentium(R)4 packages and models such that you can use gnd-sig-gnd for your
simulations. In fact you MUST use gnd-sig-vtt in a 4-way configuration.
Notice the ground-power-signal package pin pattern. This patterns assumes a
gnd-sig-vtt stackup for optimum performance.

Richard Mellitz
Intel

-----Original Message-----
From: Scott McMorrow [mailto:scott@vasthorizons.com]
Sent: Tuesday, June 05, 2001 2:47 PM
To: Yaping Zhou
Cc: Alan Hilton-Nickel; ibis-users@eda.org
Subject: Re: How to determine per length RLC in a board

Yaping,

Oh ... packages become much more interesting, because
this is where the return path transitions occur. An RLC package
model, even a multisectioned one, is based upon loop
inductances, rather than partial inductances. As a result,
it is only an approximation ... which begins to fail with lots
of simultaneous switching.

The best that one can do is to characterize a package
section, including signals, powers and grounds with some
sort of 3D partial inductance method, and then perform the
appropriate mathematical transformations to develop
IBIS compatable models which use a loop formulation.
What you will end up with, is several different models,
rather then just one, since the problem is not unique and
depends upon the switching directions of the signals
and the power and grounds.

regards,

scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com
Yaping Zhou wrote:
> Alan & Vinu:
>
> Thank your for your reply.
>
> I am actually interested in package modeling, is "good decoupling" usually
a
> good assumption in high-speed devices with a limited on-chip decoupling
> capacitance?
>
> Yaping
>
> ----- Original Message -----
> From: "Alan Hilton-Nickel" <ahilton@transmeta.com>
> To: "Yaping Zhou (r3aadv)" <y.zhou@motorola.com>
> Cc: <ibis-users@eda.org>
> Sent: Tuesday, June 05, 2001 12:26 PM
> Subject: Re: How to determine per length RLC in a board
>
> Yaping,
>
> In the SIG-GND-PWR, the PWR plane is not a return path for the signal
> layer. I suggest you model it as SIG-GND (microstrip). The high-speed
> currents will always use the GND plane, assuming good decoupling between
> PWR and GND.
>
> Alan
>
> Yaping Zhou wrote:
> >
> > Hi, All:
> >
> > If the stackup in a board is a symmetric stripline structure
> (GND-SIG-PWR),
> > the characteristic impedance is the same for switching high and low, and
> the
> > per length RLC are also the same for both switching cases.
> >
> > How to determine the per length RLC in a board with a stackup like
> > SIG-GND-PWR? The characteristic impedance and per length RLC are
> > switching-dependent, but there is no way to put two values for each
trace
> in
> > an ebd file.
> >
> > Intel uses ebd to describe packages used for Pentium processors,I have
the
> > same question there on the way to determine RLC values.
> >
> > Your help is appreciated.
> >
> > Thanks,
> >
> > --
> > **************************************
> > Yaping Zhou (r3aadv)
> > (512) 933-5803
> > Motorola Semiconductor Products Sector
> > Final Manufacturing Technology Center
> > Ed Bluestein, Austin, Texas
> > **************************************