(no subject)

Hi Folks,
     A question regarding *LVDS* I/Os with internal terminations between
the diff pins.
          When characterizing the Series resistance between the diff pins,
is the intention to capture the current prior to IBIS generation. Meaning,
is this part of Spice set up before the IBIS model is generated? or can we
just include this resistance (as a physical) model once the IBIS model is
genrated?

Thanks,
Hirut

Hirut Asfaw
ASIC I/O Developement
IBM Microelectronics Division
External: (802) 769-0652 T/L: 6-0652
hasf@us.ibm.com

 
Received on Fri Jun 15 11:02:02 2001