AW: different rising and falling Ramp dV ( AGTL+)

From: Lenski Eckhard <Eckhard.Lenski@icn.siemens.de>
Date: Sun Mar 25 2001 - 22:00:35 PST

May it be, that this should be modelled ( or is modelled ) with a driver schedule?

This is my experience with AGTL+, as the weak pullup-transistor is not always on.
It is modelled in a driverschedule, with the pulldown as the top-level-model
and the pullup as a 'sub-model'
Furthermore there appear now models, which includes the termination on chip,
( and the termination is always 'on' )
which is then modeled in the powerclamp of the top-level-model.

Eckhard Lenski
Siemens AG ICN M TC 6
Hofmannstr.51 81359 München
Tel : 0049 89 722 27776
Fax: 0049 89 722 44692
Email: eckhard.lenski@icn.siemens.de

> -----Ursprüngliche Nachricht-----
> Von: Aubrey_Sparkman@Dell.com [SMTP:Aubrey_Sparkman@Dell.com]
> Gesendet am: Freitag, 23. März 2001 23:42
> An: arpad.muranyi@intel.com; ibis-users@vhdl.org
> Betreff: RE: different rising and falling Ramp dV
>
> The case I had in mind has the dV rising about 1/3 the dV falling. The dV
> rising seems to be taken from the Rising V/T curve with 50 ohms to ground
> and the dV falling seems to be taken from the Falling V/T curve with 50 ohms
> to Vtt. There is no pullup in the power clamp for this buffer. I didn't
> ask my supplier whether the pullup was always on but I don't think it is.
> This buffer is used on a bus that has at least one pullup. This seems to be
> a little different from what you discussed; perhaps an alternate method?
> Perhaps I am missing something?
>
> BTW, my simulator seems to be OK with this as my simulations match what we
> measure in the lab.
>
> Aubrey Sparkman
> Signal Integrity
> Aubrey_Sparkman@Dell.com
> (512) 723-3592
>
>
> > -----Original Message-----
> > From: Muranyi, Arpad [mailto:arpad.muranyi@intel.com]
> > Sent: Friday, March 23, 2001 2:58 PM
> > To: ibis-users@vhdl.org
> > Subject: RE: different rising and falling Ramp dV
> >
> >
> > Sorry, I got dyslexic a bit... For the open-drain GTL buffer
> > the resistor is not connected to GND, but to Vtt, and the
> > "ON" endpoints of the Vt curve will definitely not go to GND,
> > but the "OFF" endpoints should be at Vtt.
> >
> > Arpad
> > ==============================================================
> >
> > -----Original Message-----
> > From: Muranyi, Arpad [mailto:arpad.muranyi@intel.com]
> > Sent: Friday, March 23, 2001 12:52 PM
> > To: ibis-users@vhdl.org
> > Subject: RE: different rising and falling Ramp dV
> >
> >
> > Aubrey,
> >
> > In light of the original question from Mike and my answer to it,
> > I don't expect anything different in this case. I assume that
> > the weak pullup you are talking about is always on. So the
> > two Vt curves you will make will be generated with a resistor
> > to ground, and the rising and falling edge will characterize
> > how the switched pulldown is turning on and off. The amplitude
> > of the rising and falling edge will be the same, but may not
> > start or end on the rail (GND) exactly due to the weak pullup.
> >
> > I am not sure if this answered your question, or whether I
> > understood your question fully. Did this help?
> >
> > Arpad
> > ===============================================================
> >
> > -----Original Message-----
> > From: Aubrey_Sparkman@Dell.com [mailto:Aubrey_Sparkman@Dell.com]
> > Sent: Friday, March 23, 2001 10:49 AM
> > To: arpad.muranyi@intel.com; ibis-users@vhdl.org
> > Subject: RE: different rising and falling Ramp dV
> >
> >
> > Arpad,
> > Would you comment on what you expect for something like AGTL+ which is
> > almost an open drain, but has a weak pullup? The weak pullup
> > alone can't
> > pull a 50 ohm resistor up very far.
> >
> > Aubrey Sparkman
> > Signal Integrity
> > Aubrey_Sparkman@Dell.com
> > (512) 723-3592
> >
> >
> > > -----Original Message-----
> > > From: Muranyi, Arpad [mailto:arpad.muranyi@intel.com]
> > > Sent: Friday, March 23, 2001 10:28 AM
> > > To: ibis-users@vhdl.org
> > > Subject: RE: different rising and falling Ramp dV>
> > >
> > >
> > > Mike,
> > >
> > > The reason dV can be different for rising and falling edges
> > is because
> > > the voltage swing does not have to be the same (in contrary of your
> > > statement).
> > >
> > > A falling edge ramp requires that the R_load resistor is
> > connected to
> > > the supply rail. This means that the falling edge characterizes the
> > > pulldown turning on. A rising edge ramps requires that the R_load
> > > resistor is connected to GND. This means that the rising edge ramp
> > > characterizes how the pullup turns on. Since the pullup
> > and pulldown
> > > IV curves do not have to be the same (strength), you can
> > get different
> > > swings for these two edges, hence the dV numbers will also be
> > > different.
> > >
> > > Now, if you consider an open drain type buffer, where the rising and
> > > falling edges are characterized with R_load connected to the
> > > same rail,
> > > your statement is correct, the swing will be the same, therefore dV
> > > should also be the same. However, notice that in this case one edge
> > > describes how the device turns on, the other edge describes how the
> > > same device turns off.
> > >
> > > Arpad
> > > ==============================================================
> > > =========
> > >
> > > -----Original Message-----
> > > From: Mike LaBonte [mailto:mike@labonte.com]
> > > Sent: Thursday, March 22, 2001 3:19 PM
> > > To: ibis-users@vhdl.org
> > > Subject: different rising and falling Ramp dV
> > >
> > >
> > > Many IBIS models have different values for dV in the dV/dt_r
> > > and dV/dt_f.
> > > The clipping below from IBIS spec shows an example. But the
> > > usage rules
> > > imply that dV must be 60% of the voltage swing. If the
> > > voltage swing is
> > > measured between the 2 steady-state voltages, then how
> > could you have
> > > different values for rise and fall dV? If there is variation in how
> > > simulators handle the Ramp dV values, then this may matter.
> > >
> > > Mike LaBonte
> > >
> > > |=============================================================
> > > ==============
> > > ==
> > > | Keyword: [Ramp]
> > > | Required: Yes, except for inputs, terminators, Series and
> > > Series_switch
> > > | model types.
> > > | Description: Defines the rise and fall times of a buffer.
> > > The ramp rate
> > > | does not include packaging but does include
> > > the effects of
> > > the
> > > | C_comp parameter.
> > > | Sub-Params: dV/dt_r, dV/dt_f, R_load
> > > | Usage Rules: The rise and fall time is defined as the time
> > > it takes the
> > > | output to go from 20% to 80% of its final
> > > value. The ramp
> > > | rate is defined as:
> > > |
> > > | dV 20% to 80% voltage swing
> > > | -- = ----------------------------------------
> > > | dt Time it takes to swing the above voltage
> > > |
> > > | The ramp rate must be specified as an
> > > explicit fraction and
> > > | must not be reduced. The [Ramp] values can
> > > use "NA" for the
> > > | min and max values only. The R_load subparameter is
> > > optional
> > > | if the default 50 ohm load is used. The
> > > R_load subparameter
> > > | is required if a non-standard load is used.
> > > |-------------------------------------------------------------
> > > --------------
> > > --
> > > [Ramp]
> > > | variable typ min max
> > > dV/dt_r 2.20/1.06n 1.92/1.28n 2.49/650p
> > > dV/dt_f 2.46/1.21n 2.21/1.54n 2.70/770p
> > > R_load = 300ohms
> > >
> > >
> >
> >
> >
> >
> << Datei: Sparkman, Aubrey.vcf >>
 
Received on Sun Mar 25 22:04:03 2001

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