RE: [IBIS-Users] input stimulus for extracting IBIS VT curves

Scott,

Actually IBIS v5.0 does have a few new features which attempt to
give ways to modeling those effects. They may not be perfect,
but do allow some amount of modeling them. Also, if the "built-in"
keywords are not sufficient, one can always make use of the *-AMS
languages... (I know this is a red herring to some, but it is
there, and I see more and more simulators come out with at least
Verilog-A capabilities, which is one of those languages in IBIS).

But the problem is that the behavioral modeling of the intricate
details of edge rate degradation and gate modulation effects due
to power noise is very difficult. There are lots of interrelated
interactions between the various stages of the buffer through the
parasitic capacitances (including Mr. Miller) which makes it very
difficult to write a behavioral model that includes all these
effects especially during transitions.

Arpad
====================================================================

-----Original Message-----
From: Scott McMorrow [mailto:scott@teraspeed.com]
Sent: Wednesday, August 25, 2010 12:33 PM
To: Muranyi, Arpad
Cc: ibis-users@eda.org
Subject: Re: [IBIS-Users] input stimulus for extracting IBIS VT curves

  Arpad

I agree with you on input edge rate to a buffer. Most devices have
extremely fast input rise/fall time into the predriver, since loading is

so low at this point in the circuit. What is more important for IBIS
buffer modeling is the predriver voltage rail. Unfortunately, in IBIS
there is no way to correctly model predriver power supply voltage
modulation effects, which are very real under SSO conditions.

regards,

Scott

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

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On 8/25/2010 1:26 PM, Muranyi, Arpad wrote:
> Andy,
>
> Regarding your comments on the transistor models, while it is
> a reasonable concept, it usually doesn't matter. I verified
> this by sweeping the stimulus edge rate from very fast to very
> slow, and overlaid the output waveforms, and didn't see any
> difference, other than a time shift due to the input stimulus
> reaching the threshold levels increasingly later with the slower
> slopes. This can be explained by the fact that most transistor
> buffer models have multiple stages in them, and the final stage
> is so far removed from the first stage that its waveform is
> only determined by the transistor sizing relationships between
> the stages, but not by the stimulus waveform.
>
> Your reasoning would only be true when the transistor model
> doesn't have any pre-driver stage(s), or very few of them. But
> I would strongly advise against using such transistor models
> for IBIS data extractions, because if the output waveform is
> a factor of the stimulus, then the model maker can end up making
> all kinds of incorrect IBIS models if they don't know what the
> waveform looks like on the core side of this model.
>
> Regarding the stimulus to the B-element (or the like), it is true
> that in terms of its operation it doesn't matter what the edge
> rate is, the output waveform will still be the same. But you
> need to consider that due to the slow stimulus waveforms you will
> get a certain delay in the transition. This can cause complications
> if the user forgets that the stimulus supposed to be a 0-1 volt
> waveform, and the thresholds are set to 0.2 and 0.8 if I remember
> correctly. I have seen many times people applying a source to the
> input of the B-element with a voltage swing that used the supply
> voltage value of the buffer, for example 0 to 3.3 volts. With a
> slow stimulus edge rate, the rising edge will trigger sooner than
> the falling edge very noticeably. (In other words you get duty
> cycle distortions from the IBIS model while the transistor model
> didn't do that).
>
> Even if this was handled properly by the user, similar shifting
> could occur due to the different stimulus edge rates between the
> transistor and IBIS buffer stimuli. I had people often show me
> "discrepancies" between the transistor waveforms and the IBIS
> waveforms which were due to that, and they had no clue why the
> IBIS and transistor waveforms were shifted apart in time.
>
> These are the reasons I am suggesting the use of fast edge rates...
>
> Arpad
> ===================================================================
>
>
>
>
>
> -----Original Message-----
> From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
> Behalf Of Andrew Ingraham
> Sent: Wednesday, August 25, 2010 11:14 AM
> To: ibis-users@eda.org
> Subject: Re: [IBIS-Users] input stimulus for extracting IBIS VT curves
>
> I disagree that the edge should be "as fast as possible".
>
> For the IBIS models used in HSPICE, my recollection is that HSPICE
> treats it as a switch, waiting until the (digital) input waveform
> crosses a threshold, then switching the IBIS model. The edge rate of
> that digital stimulus waveform therefore shouldn't matter ... except
> that very slow edge rate causes a known time delay before the IBIS
> modeled device switches, and extremely fast edge rates might make the
> simulation run slow or lead to convergence problems. Theoretically
> it's good to make it fast so that it works like an instantaneous
> binary switch, but there could be practical problems if you try to do
> that.
>
> For the transistor (SPICE) models, ideally you should attempt to match
> the actual waveform (edge rate and amplitude) that is at that point
> inside the IC, NOT the "fastest possible edge rate". Hopefully that
> is what the IBIS modeler did too. Using a faster edge rate than what
> those transistors normally see, makes it unrealistic.
>
> Andy
>

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