Rev 2.0 items for discussion

Greetings Gentlemen --

I've been keeping an informal list of the issues we have discussed
regarding Rev 2.0 of the spec. The following enhancements have been
proposed and, if there are no objections, I believe that we should
get closure on (i.e. officially adopt) the first two items below.

1. Proposal to add the key words [Voltage HIGH Range] and [Voltage LOW
    Range] to be used for devices with dual supplies. For specific
    details refer to Kellee Crisafulli's e-mail of July 28.

2. Proposal to add the choice of 'ECL' to the Model_type sub-parameter
    of the [Model] keyword. When this choice is made the [Pullup] and
    [Pulldown] tables become the 'high logic level' and 'low logic level'
    output characteristics respectively, and the voltages in both tables
    are referenced to the most positive (VCC) rail.

In addition, the following topics are under active discussion. As
best I can summarize:

1. In order to accurately model the effects of changing VCC on the output
    characteristics of a device, Arpad Murani has suggested using a scaling
    factor that would enable a simulator to adjust the output curves for
    VCC (and eventually temperature) on the fly. The scaling factor would
    eventually replace the 'min, typ, max' type of specification (?).

2. Also under discussion is how to best handle packages whose bond wires/
    lead frames are long enough to be considered transmission lines. It
    has been proposed to distribute the L and C values. My questions is,
    does the current spec contain all the information needed or is there
    something else to add.

     If there is anything I have missed please email the IBIS forum. Hope
     to hear from everyone Friday.

        Best Regards,
        Stephen Peters
        Intel Corp.
Received on Wed Sep 8 09:36:13 1993