Re: General Info

Jay,

Have you received the IBIS overview document? If not, send me your U.S. mailing
address and I'll get it out to you. It covers some of your questions about the
dc sweep. Regarding your second question, it is on the agenda for Friday's
phone conference, though I fear we won't bottom out on it there, since it seems
to be a somewhat volatile issue. Issues like this may indicate the need for an
earlier summit than the one being considered for DAC.

Regards,

Will Hobbs
Intel

Hello IBISers,

Being a relative newcomer to this forum, I seem to be lacking understanding
of some basic things. I'm hoping that there's some document that will
explain them, but I don't see it in the index of 1.0 or 1.1. Here goes:

1. What is the circuit topology to be used to extract the DC pin character-
    istics? If a voltage source that's swept from, say, -5 to +10 V, how
    do the results relate to those when driving a "real" load that has non-
    zero impedance? I'm a little uncomfortable with the method, but I've
    not seen any specifics about how to do it, so am making assumptions
    (you all know what results from that!). Is there some general IBIS
    document that addresses this kind of question?

2. Getting back to a question raised by Lynn Warriner a couple of weeks ago,
    I'd like to ask the signal integrity tool providers how we the prospec-
    tive customers are supposed to choose our tools... claims of "more
    accurate than xyz" are not practical to validate. I'd feel a lot better
    if there were some standard benchmarks (either net configurations or,
    better still, hardware) by which we could make choices. I recognize the
    need for tool vendors to differentiate their products, but I'm frankly
    not interested in doing detailed evaluations of several tools before
    starting a project that needs one. Any thoughts would be welcome.

Thanks for your patience.

Jay Diepenbrock
Received on Wed Feb 16 08:44:40 1994