Tips and techniques

          IBIS-persons,

          I would like to make a couple of comments about generating
          models.

          First, models should be simulated into known loads and the
          results inspected for sanity. Reversed V/I signs will show
          up quickly in the results. We generally run our models into
          three standard load topologies for a first pass sanity
          check: one pure capacitive load, one purely resistive load,
          and one "break the model" load such as the PCI Speedway load
          that is shown in the IBIS Overview. While it might be nice
          to have the more common types of errors checked for by the
          parser, there is no substitute for model validation by
          cross-correlation with silicon or netlist-level model
          simulation.

          Second, when I've been involved in releasing a product with
          some non-obvious features, we've usually provided a quick
          checklist of frequent sources of error, hint and tips, etc.
          A good one or two page document describing potential
          gotchas and hints in creating and validating IBIS models
          would be beneficial. I'd be happy to collect input for such
          a circular and post the collection to the reflector.
          Comments?

          Will Hobbs
          Intel Corp.
Received on Fri Mar 18 08:45:32 1994