SOS (reply to Dileep)

Hi Dileep,

My assumptions are:
 1) Steady state currents can be ignored since they don't contribute
    significantly to ground bounce.

 2) Internal buffer currents driving low pF gate loads can be ignored
    relative to the much large output transistor, package, and external
    loading.

 3) Internal logic switching noise can be negelected.

 4) I have done hundreds of SOS measurements with PLD's and FPGA's. The
    output buffer switching with all other internal logic held constant
    always seemed to generate the majority of the SOS energy. I admit I
    don't have any data about chips like the new advanced microprocessors.
    Although I did do some SOS tests on a 68000 about 10 years ago and the
    buffer loading was again the major contributor.

  5)Cross over region currents are small. That is the current that flows
    when both devices in a totem pole or CMOS output is smaller than the
    current resulting from the output switching the load and package
    and parasitic capacitance of the output stage. This is the one that I
    believe has the most room to cause error. But it is also highly process
    dependant.

So in summary, while there are hundreds of other effects contributing to SOS
I believe the output buffer transition is at least the major contributor.

I won't be insulted if someone want's to tell me I am full of IBIS droppings.
This is just some seat of the pant's info I have used over the years.

Kellee

Have a great day...Kellee Crisafulli, HyperLynx Inc.
Received on Wed Mar 1 19:15:07 1995