DATE: February 5, 1996
SUBJECT: 1/29/96 EIA IBIS Summit Minutes
VOTING MEMBERS AND 1996 PARTICIPANTS LIST:
Cadence Design C. Kumar*
Contec CAE, Ltd. Dileep Divekar*, Norio Matsui*
Hewlett Packard, EEsof Karl Kachigan*, Henry Wu*
HyperLynx Kellee Crisafulli*
IBM (Jay Diepenbrock)
INCASES (Werner Rissiek), Olaf Rethmeier
Intel Corporation Stephen Peters*, Will Hobbs*, Arpad Muranyi*,
John Keifer*, Aaron Tang*, Duane Quiet*,
Donald Telian*, Tim Kruchowski*
Interconnectix, Inc. Bob Ross*
Meta-Software (Les Spruiell)
Motorola (Ron Werner)
National Semiconductor Syed Huq*, Donald Snyder*, Chune-Sin Yeh*
NCR (formerly ATT-GIS) Dave Moxley*, Richard Mellitz*
NEC (Hiroshi Matsumoto),
Quad Design Jon Powell*, Chris Rokusek*
Quantic Labs (Mike Ventham)
Tanner Research, Inc. (Scott Wedge)
Texas Instruments Roger Cline*, Ben Andresen, Sri Jandhyala*,
Tareq Shahwan*, Dan Phipps*
Thomson-CSF/SCTF (Jean LeBrun)
UniCAD Canada Ltd. Celso Faia*
VLSI Technology Dick Ulmer*, Sung Oh*, Swami Gangadharan*,
Daniel Kim*, Tom Dockery*
Zuken-Redac (John Berrie)
OTHER PARTICIPANTS IN 1996:
Altera Vadim von Brzeski*
AMP Hank Herrmann
Apteq Design System Dan FitzPatrick*
Compaq Mark Leonard*
Cypress Bruce Wenniger*
Digital Equipment Corp. (Jeff Chu), (Steve Thierauf)
EIA Patti Rusher
IC Works Eric Chen*
Intergraph/Veribest Ian Dodd*
Micron Technology Brian Johnson*
MicroSim Ralph Perez
Mitsubishi Tam Cao*
North Carolina State U. (Michael Steer)
S3, Inc. Sarathy Sribhashyam*, Phap Duong*
Seimans Nixdorf Arnaud Lacariere*
Tektronix, Inc. Brock Hannibal*
TRW & Free Model Foundation Robert Harrison*
In the list above, attendees at the meeting are indicated by *. Principle
members or other active members who have not attended are in parantheses.
Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as
follows:
Date Bridge Number Reservation # Passcode
2/16/96 (916) 356-9200 2-48992 5519538
All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out
7 days before each open forum and meeting minutes out within 7 days after.
When you call into the meeting, ask for the IBIS Open Forum hosted by Will
Hobbs and give the reservation number and passcode.
NOTE: "AR" = Action Required.
-------------------------------- MINUTES -------------------------------------
INTRODUCTIONS
Will Hobbs opened the meeting and welcomed the participants. A total
of 45 people representing 24 organizations attended. A big thank you to
National Semiconductor and Syed Huq for providing the excellent local
arrangements and hosting the meeting.
MINUTES REPORT, MISC.
Patti Rusher requested that the EIA legal disclaimer note, "This meeting
was conducted in accordance with the EIA Legal Guides and EIA Manual of
Organization and Procedures." be attached to all Minutes. The January 12,
1996 minutes have been ammended to include this note at the end.
Hank Herrman submitted a clarification of the last sentence in the BIRD31
discussion. It has now been rewritten to read:
"Hank Herrmann indicated that AMP Spice models do not have any assumed
ground references. The model is designed so that any of the pins
can be used as ground or power references. You simply connect the
pins to the references, just as you would do with the actual connector."
MISCELLANY/ANNOUNCEMENTS
The reflector went down again, and Bob Ross will deal with this when
he returns. You can check email96 for missed, archived e-mail.
PRESS AND WEB PAGE UPDATES
No report. (Several papers at Design SuperCon96 the following day
mention IBIS)
OPENS FOR NEW ISSUES
Roster Update - Bob Ross
ROSTER UPDATE
Bob Ross will request roster update information. The current roster
has not tracked all of the people/organization changes and will be saved.
The new roster will contain only the 1996 supplied information. The
distribution lists at the top of the minutes will reflect only 1996
participation.
EIA /IBIS WEB PAGE
Syed Huq requested suggestions for more material and improvements of
the EIA Web page. It contains the diagrams for the EDN article and
also links to other home pages.
EIA/IBIS 1996 MEMBERSHIP
Patti Rusher sent again membership invoices upon discovering that the
first ones stated incorrect amounts. Members have 45 days upon receipt
to pay.
DAC STANDARDS BOOTH
Will Hobbs led the discussion on IBIS participation in the Standards booth
at the Design Automation Conference (DAC) in June, 1996. Jon Powell
recommended that the booth have handouts and order forms and be informally
staffed since most participants will be busy with company activities.
Pointers to other booths may be considered.
IBISCHK2 PARSER
Jon Powell will be in charge of tracking ibischk parser bugs. A created
a bug report form which will be available on vhdl.org/pub/ibis/bugs.
He new mail address ibischk-bug@vhdl.org can be used to submit bugs.
Paul Munsey and Ron Neville have completed the previously reported
problems and are awaiting instructions for the next release. This
should serve as the new baseline. Jon Powell should sent out the form.
PRESENTATIONS:
The remaining portion consists of brief notes on the presentations.
Presenters are requested to submit electronic versions of their talks
in any format to Bob Ross to be put on vhdl.org.
BRIEF OVERVIEW WITH HISTORY OF IBIS - Will Hobbs
Will Hobbs gave a brief overview and history of IBIS starting with
Arpad Muranyi's behavioral modeling, Intel's original Excel Spreadsheet
approach, and Don Telian's consolidation of formats with initial
EDA industry involvement leading to Version 1.0 in 1993 in ASCII format.
Advances continued leading to ANSI/EIA-656 (Version 2.1) plus the
Overview, Cookbook, EDN Article, s2ibis utilities (from NCSU), ibischk
utilities, reflector lists and repository of models from Intel and
National Semiconductor and other information on vhdl.org, and formal
affilation with EIA. Will listed some proposed Version 3.0 enhancements.
(More on this at the end.)
There is still need for updating the Cookbook and providing articles
on Version 2.1 features. Stephen Peters is doing an internal update,
but keeping it sanitized so it can be used externally.
Steven Peters is also working with Don Contrell of CFI on the DCL (Delay
Calculation Language Standard)
Will Hobbs reported that IBIS has an unanticipated use of conveying
buffer specification requirements internally and to customers in the
early stages of design. IBIS can serve as an electronic databook.
NATIONAL AND THE IBIS EXPERIENCE - Syed Huq
National Semiconductor Corporation (NSC) joined just after the V1.1
ratification, and pushed differential I/O, multiple rails, etc. Some of
NSC's models are generated from bench measurement. They modified s2ibis to
ns2ibis converter. It changes their NsSPICE models to IBIS, and they've used
it to convert a large library to IBIS. NSC has a library management system
for archival and controlling revisions. They have an internal IBIS home page,
and library. They've also generated training materials available on the
internal Web and publicized IBIS throughout the corporation. Several NSC
groups are generating models. The EDA industry was employed to evaluate
their models and Syed received excellent support.
All of the models National has produced are available on their Web site:
www.national.com. All of data for these components are available in the
same area, not just the models.
Syed Huq spearheaded putting an IBIS web page on eia.org, with an FAQ section,
the EDN article on IBIS, hypertext links to vhdl.org for versions of the
specication, many models, minutes archives, etc., are there, and a "virtual
poster" of member companies with potential links to members' home pages. EIA
IBIS members can have their logo on the virtual poster (a good reason to join
the committee).
Syed would like a good How-to guide to support measurement, such as measuring
package-less dV/dt, use BTL IEEE 1194.1 for C_comp measurement. He'd also
would like a way of tracking model usage on the Internet. Syed proposes
taking steps to sync up IBIS with other related standards, including JEDEC
JC-15 (package parameters) and CFI/Pinnacles/OMF/DIE/DIET efforts.
Kellee Crisafulli suggested adding a Web counter to the IBIS home pages of
NSC and eia.org. This may not give full information on who is accessing
what, but it would give a rough idea of the interest in the web sites.
Jon Powell suggested we form some subcommittees to focus on some of the
inter-specification relationships.
Syed's wish list: Create a dummy model or two that can be simulated and has
all of the IBS defined keywords and parameters with data tables. Also, a
glossary/clarification of IBIS keywords and parameters as defined in the
IBIS standard.
Bob Ross reported that there does not exist a set of models for testing
the IBIS Golden Parser.
IBIS AT INTEL: BUFFER ARCHITECTURE TO CUSTOMER MODELS - Stephen Peters
Stephen Peters gave an overview of the "Intel IBIS Experience" from the
technical side. Groups within Intel define the essential characteristics
of the interconnect between chipsets and CPUs, to bound the problem, balance
the tradeoffs between what the buffer designer can create and what the system
designer can tolerate. This results in "specification wars" until common
ground is found. To handle the communication between the system architect
and the buffer designer, IBIS is being used. This is tongue-in-cheek referred
to as "GUMBIE," or Grand Unified Model Buffer Information Exchange. The
ultimate result of the dialog between architects and designers is an IBIS
model that can be validated against silicon and shipped to customers.
Stephen gave a real example of a recent buffer definition project, where
the designers began with a simple on resistance "Ron" (linear V/I) approach.
The Ron model didn't allow a system to be designed. By switching to V/I,
they were able to meet the design challenges. This is because Ron wasn't
able to handle saturated outputs.
Stephen enumerated the issues he perceives that affect customer models: How
do you generate a "worst case" model? Are the models truly a specification
of the device? How do we guarantee a model (and do we have to?): What do
you guarantee? How do you test and characterize the model's parameters?
Obtaining skewed silicon doesn't necessarily demonstrate worst case buffers,
since the process slow skew may not be the skew that produces the slowest
I/O buffer characteristics - it may be slow for some other characteristic of
the IC.
Jon Powell: Do you really want a worst case model? The system designer may
be willing to trade off a lower yield against higher performance. Jon also
raised the issue of how to tell the customers what parameters of a model are
independent. Kellee Crisafulli suggested a corner table setup map.
MODEL PROVIDER EXPERIENCES, THE TI EXPERIENCE - Sri Jandhyala
Sri Jandhyala of Texas Instruments (TI) discussed the work going on at TI
with IBIS. Many groups within TI have developed I/O buffer models because
of strong customer demand. They are concerned by the large effort required
to generate standard SPICE models, and are concerned about the IP protection.
IBIS is attractive, too, because of the vendor independence, reduced cycle
time. Customers are asking for IBIS models by name.
Sri listed many companies that have explicitly asked for IBIS models, such
as Apple, Bay Networks, HP, IBM, Intel, LG Semiconductor, Unisys and others.
TI has allocated resources to steer their IBIS efforts and support IBIS.
They are developing internal tools to automate model creation process. TI
is committed to the support and development of IBIS. IBIS model generation
is to be integrated into the product development flows.
Current issues: standardizing the process, characterizing the models,
validating the models, establishing common procedures and improving the
coordination between work groups.
Question: Whom does a customer contact to get model information? Answer:
The TI Web page will have links into TI IBIS information. Sri's e-mail is
srij@ti.com.
Company policy is not to release IBIS models publicly on the Internet. This
appears to be because management isn't yet comfortable with the models. TI
has around 30 models available so far.
Dave Moxley indicated he'd like more ready access to the models, as he
might use the models as a method to decide whether he wants to buy the TI
components.
USING IBIS MODELS IN SYSTEM DESIGN - Dave Moxley
Dave Moxley of NCR (formerly AT&T-GIS) reported that NCR develops their
models through simulation and validates them via measurement.
NCR is in the massively parallel and SMP server business. They stress
reliability and quality. They routinely develop with sub-nanosecond timing
margins, with bus speeds up to 100 MHz today, and higher in the future.
Critical analysis goes into board design and ASIC design. Both noise margin
and timing margins have shrunk dramatically over the years that NCR has been
doing these designs.
Signal Integrity questions: How many power and ground pins are required?
What layout constraints apply, how many bypass capacitors and of what type?
What layout topologies will be required? How fast can a design operate
reliably? What buffer strengths are required to insure reliable operation?
How will normal manufacturing variation affect performance?
Regarding manufacturing, IBIS is used here to play what-if games, which is
why he is interested in obtaining IBIS models over the spread of process
variations. They use both 2D and 3D solvers.
Dave showed the general flow they go through in doing the design from
concept through what-if to layout and verification.
They've seen good correlation between SPICE, IBIS and silicon in test
silicon, test vehicles and components from ASICs to clock distribution
devices, buffers, memory and processors.
Question: How do chip specications relate to IBIS Models: setup, hold,
clock to data, access time, clock skew, buffer delay?
During their design analysis, they look at every circuit, examining for
corner case variations, timing, crosstalk, threshold violations and other
anomalies.
They would like industry wide support for IBIS, with vendor contacts at each
company and public library maintenance. They are considering making IBIS
model availability a requirement in contracts with the vendors they are
dealing with.
Other issues included silicon corner verification, slow-n/slow-p may be
fastest edges. Also included are drivers with feedback. Sometimes there
are application specific work-arounds. They would like to be able to obtain
IBIS models from customer supplied parameters of Voltage, temperature and
load. And, they'd like to know the relation between the IBIS models and the
board level related timing specifications.
MODELING LOSSY TRANSMISSION LINES - C. Kumar
C. Kumar of Cadence presented modeling issues related to modeling lossy
transmission lines. The industry trends that concern him are increasing
speeds, 200 MHz and beyond, which drives higher and higher slew rates;
shrinking sizes; and High DC and Skin Resistance. At higher frequencies,
the resistance of a conductor can increase by an order of magnitude.
The classic transmission line model begins with a segmented RLC
representation, with the number of segments going to infinity. A lossy
transmission line adds frequency dependent losses. The incident and
reflected waves encounter different resistances due to the differences in
high frequency components of the two waves.
Fundamental challenges are in how to approximate these effects. They use a
"rational approximation." Stability is one potential pitfall. He gave an
example of an ECL transmission line running at 400 MHz. He compared a lossy
transmission line simulation with segment and lossless models, demonstrating
that noise margin losses are shown by the lossy transmissions and not by the
other two. The lost noise margin of 20 mV is significant in ECL designs.
He also showed an example of a CMOS circuit running at 200 MHz showing that
at 200 MHz the effects are not nearly as pronounced as at 400 MHz.
Kumar showed that modeling bonding wires with inductors versus skin resistors
produces a less-damped waveform than the skin effect resistor, which
correlates better with actual components.
He concluded that at higher speeds, frequency dependent effects become
significant, particularly with respect to noise margins.
Jon Powell noted that if and when we ever get to modeling large networks,
such as MCM, lossy transmission lines will be a significant contributor to
accuracy.
EGG8: MODELING PACKAGES WITH PHYSICAL DESCRIPTIONS - Kellee Crisafulli
At Syed Huq's request, Kellee Crisafulli also discussed the Visual IBIS Editor
The Visual IBIS Editor is a Windows based standard text editor including
special features for source code editing, with the syntax checker built in.
At any point, you can check the syntax, like a spell checker. There is also
a graphical viewer for VI tables, and rising and falling waveforms. Finally
there is an IBIS file creation wizard, a skeleton file for either V1.1 or
V2.1 that can be used as a foundation model to begin developing the model.
It can be used on Windows 3.1, Windows 95 or Windows NT, but not UNIX. It
is available at http://www.hyperlynx.com for download for free, but HyperLynx
asks that models that are created on it are made publicly available.
Kellee then discussed Egg 8: Physical Package format for IBIS. There is
presently no standard way to create or deliver signal integrity models for
integrated modules, such as SIMMs and MCMs. SIMMs from different vendors
for the same target socket are laid out differently and therefore behave
differently. Kellee proposes a SIMM module physical package file at the
top, linked to individual IBIS files below.
After looking at the state of the art, Kellee concluded there are no standard
PCB formats that PCB tools read and write today without purchasing special
translators. Existing standards, such as EDIF, are too complex. Instead,
Kellee proposes a simple ASCII PCB description. He gave an example of a 4
layer package. Starting with the stackup (signal and power, etc., layers
can be defined), pad stack, layer to IBIS model association, and an
interconnectivity portion that defines specific nets with bias, pad stacks,
segments, pins. The segments are defined by their endpoints. The ordering
is "unimportant." One issue discussed was the problem of line segments that
connect, but whose x,y endpoint coordinates don't always coincide due to
trace length, trace overlap, via width, etc.
Kellee contends that the IBIS committee needs to endorse a standard for
physical descriptions.
Kellee used curly braces instead of square brackets to make it simpler for
parsing, but he is open to alternatives.
Cutouts in the ground plane can be modeled. There is no support for cross-
hatched planes, however.
Several wondered if it would be possible to specify min and max for such
things as dielectric constants and trace width.
Don Telian expressed concern that unless there were netlisters to generate
these files for a given format, the SIMM suppliers will not use it. Jon
Powell and Kellee said that there are lots of people that create writers for
new formats for as little as $10K.
Jon would like to make sure there is something in the specication that ensures
that non-simulated conditions will not meet the specification. E.g., a net
that is two completely discrete segments would be illegal.
Ian Dodd added zero length nets should be checked. Kellee hesitates to add
these checks because all layout packages today put out certain amounts of
garbage. There is general agreement that this is a problem, but not on
where to put the burden of guaranteeing that such bad data doesn't torpedo
the simulation.
BIRDs 28.3, 32: MODELING PACKAGES WITH ELECTRICAL DESCRIPTION -
Stephen Peters and C. Kumar
Stephen Peters discussed BIRD 28.3, wherein an electrical approach is taken
to describing packages. He showed drawbacks with the current IBIS
methodology that are addressed by the BIRD. He also identified a problem
in modeling BGA packages because of a plating stub that can't be represented
in a standard section by section description.
C. Kumar said that two values to an electrical description are: it can't be
reverse-engineered as a physical description can, and the data can be very
compactly represented. Kumar filed BIRD 32 as an extension to BIRD 28.3 to
add arbitrary coupling and handle an arbitrary number of sections compactly.
The coupling information is represented in a named matrix and multiple
models can be referenced by any number of models.
Question: Is a pure physical description sufficient so we don't need the
electrical version, or do they each have a place? The consensus seems to
be that each has value. There may be cases where one would be preferred
over another. For example, there are cases in packages where the signal
path may not be planar, causing the physical description to be inadequate.
If they both are supported, Ian Dodd would like to see the same syntax be
used for each type of representation.
The discussion highlighted a number of issues the forum will have to resolve
before incorporation into the specication.
BIRD 31: CONNECTOR MODELING - Bob Ross
Bob Ross of Interconnectix discussed BIRD 31, extending IBIS into connector
utility. Bob has already decided BIRD 31 has to be replaced by a new one
that Bob will write soon. Connectors are usually described by lumped
sections, transmission lines, sections and edge rates, their symmetry, pad
capacitance and the ground reference. It usually is supplied in SPICE
subcircuit format and also for single line connectors, in a data sheet.
Karl Kachigan of HP asked how to deal with connectors that have mated pairs
when they're not mated, such as backplanes. This could be handled in a manner
similar that decribed by BIRD30 which has been approved. Normally unmated
models are not provided.
Bob showed an actual right angle connector with multiple rows and columns
and different path delays.
He then showed what would be in a SPICE model format with coupled pins. The
pins are grouped, the descriptions are in sections and edge rates, with
symmetry (e.g., 3 inductor, 2 capacitor sections), making it not directly
convertable to transmission line format needing an equal number of L's and
C's. Other Details such as explicit or implicit ground references,
pad capacitance, fins (connected metal planes dividng groups of pins),
etc. need to be considered. Exact pin mapping to actual connector circuit
pins are details critical to the EDA industry for correct path simulation.
So the set of subcircuits must accurately present pin descriptions that
can be used for any pin.
Spice subcircuit connector models are derived from field solver extractions
and converted into equivalent L and C transmission line sections. Exact
pin mapping of the circuit board contact of all pins to the connection
path is critical to the EDA industry for correct path simulation. Details
on certain pins (or treatment of missing pins at ends and other places
due to construction by modules) may be missing. Thus connectors are
suitable for IBIS syntax because of the exact pin mapping and because
IBIS would use the field solver matrices directly. The alternative is
to reverse engineer models from Spice Models.
Bob will revise BIRD31 to have one or two pin columns for numbering,
cross-connection, and symmetry variations, will embed cable within
connector model groupings, and offer pad capacitance options. Larger
models would have to be auto-generated by expanding from a known set
of comprehensive field solver extractions.
STORED CHARGE MODELING, DIODE DELAY DISCUSSION - Jon Powell, Bob Ross
Jon Powell of Quad Design opened the discussion on diode transit time.
Charge storage results from excess minority carriers injected across the
junction in forward bias. Transit time (TT) represents the minimum time
required to store or remove charge from the junction. For moderate or more
forward bias, the stored charge dominates.
Jon recommends the reference "Semiconductor Device Modeling with SPICE," by
Antongnetti and Massobrio. This book has a good model of this effect by
relating a capacitance in parallel to a current sinking diode, with the
parallel net in series with a resistor Rs. The TT effect can create heavy
but delayed ringing, an effect missed without the diode TT being modeled.
Jon proposes we add TT support to IBIS. Stephen asked if there was a
measurement technique that could derive TT. Jon says that this is being
done today, so there is a way. He also noted that the diode that has the
intrinsic capacitor is the static protection diode, which swamps the effects
of input and output capacitances of the buffer structure.
Bob Ross continued the presentation. He showed that Ct can be derived from
the standard diode equation to be a proportional to TT * Id * (q / KT).
Id is the diode current, q is charge, K is Boltzmann's constant, and T
is absolute temperature. The theoretical dependence on temperature is
motivation to have typ, min and max specifications.
Kellee Crisafulli asked whether we should specify TT or Ct? He feels that
Ct can be measured by forward biasing the diode at a specified current and
measuring the capacitance.
Bob and Jon provide a BIRD to bring this issue to closure.
EGG 6: DETECTING CMOS VERSUS TTL - Jon Powell
Jon Powell has concluded that just knowing the technology is not necessary
or sufficient. Rather, the standard 50 ohm measurements do not adequately
demonstrate TTL characteristics. He recommends instead 500 ohms to ground
and 7 ohms to power. He bases this on where the load lines intersect the
pullup and pulldown tables to best isolate the pullup from the pullup
characteristics for the rising and falling transitions. This doesn't violate
the IBIS specication, but implies a needed change to the cookbook. Even
more loads allow greater accuracy, but these two are sufficient to produce a
good model. For CMOS, the 50 ohms to power and 50 ohms to ground is still
sufficient. Jon will help contribute to the cookbook.
DOUBLE COUNTING AND OTHER MODEL GENERATION ISSUES - Arpad Muranyi
Arpad Muranyi of Intel discussed double counting that can happen easily
with internal pull-up resistors. The pull-up shows up in both the power
and the ground clamp portions of the model in extractions. This results in
double counting the effect. Arpad proposed an algorithm which eliminates
this effect.
The double counting effect is minor but might affect the DC float voltage
of a net. Arpad will write this up and submit it to Kellee Crisafulli for
inclusion in the cookbook.
Another issue Arpad addressed was the way pull-up and pull-down IV curves
are defined, which is the difference between floating and on values. These
curves add correctly only if the same reference values are used at the time
of measurement. He used a 5-volt safe 3.3 V input device to illustrate the
problem, as there may be two different reference voltages at different times.
A third issue is the derivation of the value of the R_load sub-parameter. For
backward compatibility, the ramp keyword is still required in V2.1. The ramp
could be derived from IBIS 2.1 without this keyword. R_load is required if
not equal to 50 ohms. Deriving the ramp number is problematic if all
R_fixtures are not the same.
Both of these cases are worth noting in the cookbook. Kellee says they've
already run into this problem with some V2.1 models, and since it is
superseded by the ramp tables, they ignore it. One possible solution for
V3.0 is to add an R_fixture to the ramp.
RAIL, RULES AUGMENTED INTERCONNECT LAYOUT SPECIFICATION - Donald Telian
Don Telian of Intel introduced the RAIL specification aimed at automating
the PCB layout and simulation process. It is an industry-wide initiative.
Circuit simulation has become critical as speeds increase, with flight
times being a significant percentage of the clock period, and crosstalk
increasingly problematic due to ever finer pitches.
RAIL addresses the gap between good simulation and manufacturable
boards. The three elements of system design are physical, logical and
electrical. RAIL complements IBIS to complete the electrical piece of
the pie. Rail is a "container" for electrical constraints.
RAIL has been developed to an initial specification level by Intel and five
simulation vendors. Most tool vendors already have elements that can accept
RAIL data, which is an electronic (ASCII) version of layout guidelines,
providing clear communication of electrical constraints, such as maximum
trace length, acceptable flight time skew, etc.
Don described the RAIL syntax, which looks like IBIS syntax. Don obtained
permission from EIA to make the two look this similar. Typical keywords
include [Stackup], [Group Nets], [Topology], [Budgets] (flight times, max
overshoot, crosstalk limits), [Clock Skew]. He provided a typical example.
RAIL can be used as a post-processing tool, where the route is done,
then checked out and the PCB is modified and the post-processing is done
again, re-iterating until everything comes out clean. It can also be
used interactively, where nets are hand routed while the simulator is
running in the background to tell the user if there is a problem with
the net in real time. The third approach takes a netlist, IBIS and RAIL
and feeds an autorouter with integrated simulation, resulting in a nearly
effort-free and fast layout.
VHDL has volunteered to make resources available for RAIL on vhdl.org,
including rail@vhdl.org, rail-info@vhdl.org and rail-request@vhdl.org
reflectors. There are slides, minutes, the V1.0 version of the specification,
etc. are available on vhdl.org under /pub/rail. [Note, the rail reflectors
have been experiencing similar difficulties as the ibis reflectors.]
The five EDA vendors that put the specication together with Intel are
Cadence, Mentor, Quad Design, HyperLynx and Interconnectix.
Don would like the simulators to extract RAIL files from successful
designs for later use. He pointed out the value of the RAIL data for
sustaining engineers, who can go back to the original design database
and see if it met constraints, without having to track down the
original engineer on the project.
The RAIL committee will meet on a monthly basis, and hopes to have
demonstrations at DAC. RAIL files will be released from PCD at Intel,
along with the IBIS models. A RAIL golden parser will probably be needed
for RAIL.
USEFUL NON-SIMULATON DATA INCLUSION - Jon Powell
Jon Powell asks: Is there a place in IBIS for information that doesn't
affect simulation? Threshold is already included, so Jon explored
additional ones. Timing related information could include additional
thresholds, other timing information, such as pin-to-pin information.
Several others are already addressing this, including DIET, DCL. Another
idea is to correlate between IC timings and the IBIS models. E.g., an
annotation could be made in the IBIS file that a particular specification,
such as Tco, was made with a particular corner of the IBIS model.
Perhaps we should expand the threshold to include a rising and a falling
threshold, which could handle hysteresis. The 54/74LS132 defines a Schmitt
trigger with a vlow and vhigh for the rising edge, and a vlow and vhigh
for the falling edge.
Component reliability could be addressed by adding information on low and
high voltage requirements - overshoot limits and time in threshold limit.
Other factors include: monotonic requirements, pulse size requirements,
illegality of leaving the input floating.
John will submit a BIRD.
BUS HOLD CIRCUITS AND EIA JEDEC JC40 - Bruce Wenniger
Bruce Wenniger of Cypress Semiconductor is involved with the JEDEC JC40
committee which is working to make sure components from different
manufacturers are interchangeable. He discussed bus hold, in response
to the discussions on the reflector.
Bus hold is the ability of an input or output pin to retain the last
valid logic state after the source driving it enters the high impedance
state. Such circuits reduce noise in a system, and improve hold times.
The bus hold circuit is particularly important with CMOS devices which
can float to their linear region and draw excessive current and possibly
self-destruct. Bus hold circuits also eliminate the need for pull-up
and pull-down devices, reducing power consumption. This is a real
benefit for lap top computers. The circuit is simply a weak output
connected to the pin with positive feedback.
There is no JEDEC standard for 5V logic. The de facto standard was
established by the TI ABT Series. The LVTTL standard is currently being
debated by the JC40 committee, which consists of a number of IC vendors.
OPEN DISCUSSION: IBIS 3.0 POSSIBILITIES, WISH LISTS - Will Hobbs
Will Hobbs of Intel led the closing discussion on what people want in
Version 3.0 of IBIS and other areas. The results of the discussion are
summarized:
Will listed the top technical enhancements for Version 3.0 that the
group proposed:
Packages and connectors:
Physical description
Electrical description
MCM support
Diode modeling (transit time, charge storage)
Multiple drive level buffer-dynamically switched or staggered turn-on
Feedback support (e.g., dynamic pre-driver effects such as gate modulation)
Multiple drive level-selectable (done)
Balanced drive outputs (already can be handled)
Scaling of parameters (possibility)
Other ideas:
Refine SSO (simutaneous switching outputs)
Power modeling
Support for static timing
New challanges for higher speeds
The informational and technical clarification and model availablity
wishes were:
Model validation guidelines
New Modeling Cookbook
More models
Clarification of worst case/best case?
Presentations, overviews, intros to IBIS
Press Release after summit
Other ideas:
Enhance s2ibis, golden parser
Create awareness of library
Move IBIS into new uses & arenas
In addition to Intel and National, the attendees indicated that the
following companies also have developed IBIS models: S3, Micron, Cypress,
TI, and VLSI.
The attendees felt that the most important issue to address was model
validation. That is an obstacle to many companies releasing models
widely. Kellee Crisafulli reiterated his offer to provide a HyperLynx
simulator to companies willing to develop and make public IBIS models.
CELEBRATION DINNER:
Thirteen people celebrated the Adoption of ANSI/EIA-656 at dinner.
NEXT MEETING:
The next telephone meeting is set for Friday, February 16, 1996.
==============================================================================
NOTES
IBIS CHAIR: Will Hobbs (503) 264-4369, Fax (503) 264-4210
will_hobbs@ccm.jf.intel.com
Server Chipset System Validation Manager, Intel Corp.
2111 NE 28th M/S JF1-57, Hillsboro, OR 97124 USA
VICE CHAIR: Jon Powell (805) 988-8250, Fax: (805) 988-8259
jonp@qdt.com
Transmission-Line Products Manager, Quad Design
1385 Del Norte Rd., Camarillo, CA 93010
SECRETARY: Bob Ross (503) 603-2523, fax (503) 639-3469
bob@icx.com
Modeling Engineer, Interconnectix, Inc.
10220 SW Nimbus Ave, K4, Portland, OR 97223
This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.
The following e-mail addresses are used:
ibis-request@vhdl.org
To join, change, or drop from either the IBIS Open Forum Reflector
(ibis@vhdl.org), the IBIS Users' Group Reflector (ibis-users@vhdl.org)
or both. State your request.
ibis-info@vhdl.org
To obtain general information about IBIS, to ask specific questions
for individual response, and to inquire about joining the EIA-IBIS
Open Forum as a full Member.
ibis@vhdl.org
To send a message to the general IBIS Open Forum Reflector. This
is used mostly for IBIS Standardization business and future IBIS
technical enhancements.
ibis-users@vhdl.org
To send a message to the IBIS Users' Group Reflector. This is
used mostly for IBIS clarification, current modeling issues, and
general user concerns.
ibischk-bug@vhdl.org
To report ibischk2 parser bugs. The Bug Report Form Resides on
vhdl.org in /pub/ibis/bugs/bugform.txt along with reported bugs.
Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page:
http://www.eia.org/eig/ibis/ibis.htm
Check the pub/ibis directory on vhdl.org for more information on previous
discussions and results. You can get on via ftp anonymous, "guest" login from
telnet or dial-in (415-335-0110), or send an e-mail request to the automatic
archive server, archive@vhdl.org.
"IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for
use at trade shows.
==============================================================================
Received on Mon Feb 5 11:33:11 1996
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