Re: Egg10 Implementation

Kumar,

C. Kumar wrote:
>
> That is a relative check. I have seen models which do not settle to anything anything near the dc voltage. I mean the dc voltage defined by the VI table. (it should be the true dc , isn't it?). I think it is necessary explicitly clarify whether you are talking about dc voltage or steady state settling voltage.

The test is designed to enforce what the spec says:

      A waveform table must include the entire waveform;
      the first entry (or entries) in a voltage column
*** must be the DC voltage of the output before switching
      and the last entry (or entries) of the column must be
      the final DC value of the output after switching.

The spec says "MUST BE", I think the spec should be more explicit and
say something more along the lines of...

The first/last waveform point voltages must lie within X Volts of the
given fixture loads interection with the appropriate (TYP/MIN/MAX) VI
curve where X = (first Waveform voltage point - last Waveform voltage
point) * 2%.

The models you mention that don't settle to anything near dc appear to
be in violation of the current spec. Correct? If we can decide on a
percentage, be it .01%, 1%, or 5%, then ibischk2 can enforce the spec
with the added code.

In the orginal example below, "v_dc_for_load" refers to the intersection
of the load line with the DC vi curve and thus would enforce a
correlation between each AC waveform endpoint and the VI curves.

> > Example Waveform:
> >
> > Begins: (0ns, 0.0V)
> > Ends: (9ns, 4.0V)
> > Load: 50 Ohms, 0.0V
> >
> >
> > For 2% agreement, the v_tolerance = 2% * (4.0 - 0) = .08V
> >
> > So model passes if...
> >
> > -0.08 < v_dc_low_for_load < 0.08
> >
> > AND
> >
> > 3.92 < v_dc_high_for_load < 4.28
> >
Received on Thu Oct 31 11:13:47 1996