DATE: February 5, 1997
SUBJECT: 1/20/97 EIA IBIS Summit Minutes, Santa Clara, California.
VOTING MEMBERS AND 1997 PARTICIPANTS LIST:
AMP (Ray Ziesse), Jeff Walden*
Applied Simulation Technology Dileep Divekar*, Norio Matsui*
Cadence Design C. Kumar*, Don Telian*
Cypress Bruce Wenniger*
Hewlett Packard, EEsof Karl Kachigan*, Henry Wu*
HyperLynx Kellee Crisafulli*
INCASES (Olaf Rethmeier)
Intel Corporation Stephen Peters*, Arpad Muranyi*,
Interconnectix (Bob Ross)
Meta-Software (Sanjay Gangal)
Mitsubushi Tam Cao*
Motorola Ahmed Omer
National Semiconductor Syed Huq*, Cheng-Yang Kao*, Mike Brisbi*
Peter Laflamme*, Kevin Smith*,
NCR (Dave Moxley), Richard Mellitz*
NEC (Hiroshi Matsumoto)
Quad Design Jon Powell*, Chris Rokusek*
Quantic Laboratories (Mike Ventham)
Texas Instruments (Sri Jandhyala), Thomas Fisher*
Thomson-CSF/SCTF (Jean LeBrun)
UniCAD Canada Ltd. (Celso Faia)
Veribest Ian Dodd*
VLSI Technology (Dick Ulmer), Hrish Patel*, D.C. Sessions*,
Zuken-Redac (John Berrie)
OTHER PARTICIPANTS IN 1997:
3M Fran Hart*
Actel Scott Schlachter*
Acuson & Free Model Foundation Richard Munden*
Alcatel John Fitzpatrick*
Ansoft Eric Bogatin*
Apteq Design Systems Dan FitzPatrick*
Compaq Weston Beal*
Digital Equipment Corp. Jeff Chu
EIA Patti Rusher*
EMC Fabrizio Zanella*
Micron Technology Brian Johnson*
Molex Gus Panella*
North Carolina State U. (Michael Steer)
S3, Inc. Porsh Shih*, Jarathy Jribhashyam*
Ultratest International Charles Im*
In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.
Note, refer to the January 10, 1997 minutes for the last listing of the
1996 IBIS Open Forum participants.
Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as
follows:
Date Bridge Number Reservation # Passcode
2/14/97 (916) 356-9200 3-81822 3973256
All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out
7 days before each open forum and meeting minutes out within 7 days after.
When you call into the meeting, ask for the IBIS Open Forum hosted by Will
Hobbs and give the reservation number and passcode.
NOTE: "AR" = Action Required.
-------------------------------- MINUTES -------------------------------------
MINUTES NOTES:
These minutes are constructed from raw/unedited notes taken and distributed
by Jon Powell. The minutes capture some highlights of an all day face-to-face
meeting where much of the technical content is in the presentation material
itself. The presenter's are welcome to submit corrections and clarifications
to these minutes, as needed. Syed Huq and Jon Powell will be working on
making the presentations available in computer readable formats on vhdl.org
for FTP or Browser access. These minutes contain some corrections received
after Jon's notes were distributed.
Jon noted that this was a well attended meeting with representatives from all
of the various areas of IBIS interest including IC manufacturers, connector
manufacturers, EDA vendors, and end users. The presentations were informative
and covered a variety of topics.
Finally, we give special thanks to Syed Huq and National Semiconductor for
hosting the IBIS face-to-face meeting. National provided an excellent room
and superior refreshments.
INTRODUCTIONS - Syed Huq, National Semiconductor
Syed Huq, National Semiconductor: Presiding
Jon Powell, Quad Design: Acting Secretary
Patti Rusher, EIA: EIA Representative
REVIEW OF SUMMIT AGENDA, OPENS FOR NEW ISSUES - Syed Huq
A question was raised regarding who is providing models. Jon Powell, who is
serving as Librarian, commented that he will run QA checks on any model that
is e-mailed to him at jonp@qdt.com. He also is soliciting models to be added
to the IBIS reflector. Jon has not received any new models for release during
the last eight months (except from Arpad Muranyi).
ANSI/EIA-656 (IBIS) OVERVIEW - Syed Huq
Syed Huq presented an overview and IBIS roadmap and discussed the usage of
the IBIS reflectors for communication.
Jon Powell indicated that IBIS Open Forum Member companies can add or update
your company logo on the IBIS Poster page of the EIA/IBIS home page. Send the
logo to jonp@qdt.com. It should be in bmp or tiff format and have a size of
about 800x200 pixels. Bigger is better since Jon can size it down.
EIA MEMBERSHIP AND IEC UPDATE - Patti Rusher, Electrical Industries Association
Patti Rusher reported that there are 23 Official EIA/IBIS Members to date.
Committee Membership is $500.00 per year. Membership applications are
available from Patti and will soon be available on EIA/IBIS Web site. Bills
for 1997 were also distributed at the meeting.
IBIS will be represented at the Design Automation Conference (DAC) in June,
1997 in the EIA booth.
Regarding EIA Web page usage, IBIS is number two in the EIA on hits and has
over 7000 hits since page inception.
IEC Update: Patti reported that IBIS is going through the international
technical committee. IBIS will be assigned to Hilary Kahn. The goal is
to have out as a full standard in the next two years.
[Update from Patti: IBIS did not pass international standardization at the
last IEC TC93 US TAG meeting because only three countries agreed to work on it
(USA, Japan and UK with Denmark abstaining) and five are required. Several
other countries will be approached.]
IBIS MODELING AT ALCATEL - John Fitzpatrick - Alcatel CIT
John Fitzpatrick indicated that Alcatel makes telephone switches. Alcatel has
committed to building a large library of IBIS models. They have done signal
integrity analysis in the past by hand using Bergeron diagrams. The goal
with IBIS is to use models for simulation and extracting information to
create design rules.
John has found that the IBIS he uses that are not from the vhdl.org
directory contain errors in all cases (100%). Therefore Alcatel is
generating and checking the IBIS models themselves in a signal integrity
laboratory.
They want to use IBIS models to do constraint driven routing and also to use
the IBIS files in a data base to extract information for design rules. An
example of a question is: Do 3 volt devices need protection? Another use
is to help with crosstalk control and route constraint generation for
correct-by-design routing. IBIS models would provide the component series
resistance to be used in conjunction with the proper series termination.
John's wish list for IBIS extensions are:
1) Series components. (Very important)
2) Non-monotonic IV curve models.
3) R,L,C description capability.
4) BUS Switch Models (This is a very important issue)
Alcatel wants to keep all models in IBIS format, but right now they are being
forced to keep models in multiple formats because IBIS does not support the
above extensions.
John's less important wishes are:
1) Easier to understand IV curves: John suggests the need for new keywords
that support pure measurement derived values and formatting and let the
simulator do the necessary subtractions, etc. (A comment from the
audience suggests the development of a better editor on input method.)
2) More background information in the model: Contact information, Brief
description of the component, or URL to the component description.
3) Unique buffer names: Guidelines on buffer naming - each supplier should
use a unique meaningful name.
4) Model Verification.
5) Long term goal: Full Electrical Specification (don't need data-sheets).
6) Recommended paper data-sheet format for representing IBIS models.
7) Better specification of minimum data to have in IBIS models.
8) IBIS as a specification tool.
Other suggestions include:
ASICs (to allow for a choice of output buffers)
Second sourcing (give us a part that matches this model)
Industry-standard I/O (Golden IBIS models representative of industry
standard technologies (LCT, LVC, AC, FAST, Memories etc.)
VISUAL IBIS EDITOR - Kellee Chrisafulli
Kellee Chrisafulli offers the HyperLynx Visual IBIS Editor free from several
websites. He is seeking user inputs on how to improve the Editor. It
works with Windows 3.1, 95 and NT, but runs best on 95 and NT. It has
a built in IBIS Version 2.1 and 1.1 syntax checker and an IBIS Skeleton
generator. Built in viewers allow displaying the various tables graphically
to assist in debugging the data. However, these tables cannot be edited
using the viewers. The Editor is available on http://www.hyperlynx.com.
Sheets were passed out to the audience for inputs concerning feature updates
and suggestions.
Suggestions given by audience include:
1) Show loading conditions on waveforms.
2) Overlay multiple curves for comparison of different models.
3) Don't show clamp of data beyond data range. Just show the end of the
data.
4) Veribest might provide a spice2ibis converter in Windows NT executable
format.
5) Remove the Control-M characters from files because they are not allowed
in IBIS. (Is this true?) - [Answer - DOS formatted data is permitted
and most parsers will ignore the Control-M character.]
6) Allow graphically editing of the tables.
7) Provide a pop-up menu with blanks for all input values.
Comments to Kellee can be sent directly to kellee@hyperlynx.com.
One comment is that IBIS standard needs to define how to interpret data that
is beyond the end of the IBIS data range. Another comment is to contact Ian
Dodd regarding putting his version of spice2ibis for Windows NT on an IBIS
Web Site.
SIGNAL INTEGRITY AND IBIS - Don Telian, Cadence
[Note, this presentation was also given at Design SuperCon97 as "Signal
Integrity Engineering in High-Speed Digital Systems" and was voted the
best presentation. Don's background includes authoring both the initial
IBIS and initial RAIL specifications and chairing the initial public forum
committees for both devepment activities.]
Don Telian, a Signal Integrity Engineering in High-speed Digital Systems
Surveyed 5 managers of SI groups and put their feedback in this presentation.
(See Don's slides and/or the Design SuperCon97 High-Performance System Design
Conference proceedings, pp. HF213-1 - HP213-17 for the actual presentation.)
The goal of this presentation is to define the SI engineer. Electrical
description is moving from a static form to a dynamic form. Don presented
seven roles of SI engineer:
1) Pioneering and Defining
2) Partitioning and Approximating
3) Modeling and Measuring
4) Design and Optimizing
5) Quantifying and Verifying
6) Reducing and Simplifying
7) Correlating and Debugging
In conclusion one must resolve to use good judgment rather than to whine.
PROBLEMS REPRESENTING ABT MODELS USING IBIS - Jon Powell, Quad Design
Jon Powell shared that the TI Spice models for the ABT series demonstrates
a charge pumping and load dependent IV phenomena beyond what can be
represented in the current IBIS format. Jon showed a simplified circuit
and gave some simulation examples to illustrate the effect. Jon plans to
post a full report to the IBIS reflector for further discussion.
AN IBIS SURVEY - Karl Kachigan, Hewlett Packard - EEsof
Karl Kachigan reported the results of a survey questionnaire he had issued
earlier on the IBIS reflector. The survey asked how people develop models,
and the results show:
1) Most use Spice to develop models (based on 100% of responders derived
IBIS models from Spice).
2) There is opportunity for commercialization of SPICE to IBIS converter
(but people are not willing to pay a high price for such a converter).
3) Four out of seven responders said they did use some measurement
techniques to validate the simulation.
4) The generation of models is usually not part of the budget.
MODELING EARLY CLAMPS IN IBIS - Arpad Muranyi, Intel
Arpad Muranyi reported on Intel work on "Integrated Termination for Low Power,
Low Cost, High Speed Signaling" to put into chips.
To be competitive in the personal computer market, Intel needed to develop a
a low cost desktop chip set solution for the P6.
Currently the GTL bus needs two terminators. This cost too much money and
uses to much current. Intel has found a good technique that works in both GTL
and CMOS. It lets you get rid of the resistors.
Arpad showed a worst case circuit: A Tee topology circuit with termination
in the middle. Terminating it at both ends causes problems. What is needed
is a termination with a special IV curves with no currents at VOH and VOL. A
solution is to use Early clamps to match diodes to the desired curve.
In GTL systems, VOL drifts because it varies on buffer strength (and the
strength of the pullup device).
Static Early clamps are easy to model by inserting IV curves into the clamps.
Dynamic curves are harder. Perhaps shift a IV curve as controlled by a VT
curve. But the shifted IV curve might not be the same as the original IV
curve. The timing is completely dependent on the implementation of the
method, which is not defined. Arpad wants to come up with a IBIS
description method that encompasses all possible implementation techniques.
A suggestion was made to try and fit this into the Multi-staged Outputs
BIRD35.3. BIRD35.3 would have to be modified to add a multi-receiver
technology with a threshold test. Arpad will open this discussion on the IBIS
reflector.
BIRD36.D - Stephen Peters, Intel
Steven Peters introduced BIRD36.d (which is work in progress by an off-line
Package Committee to develop BIRD36.1 for IBIS Open Forum) by stating its
intended scope:
Simple board descriptions (SIMMs)
Connectors (coupled and uncoupled)
Complex (coupled) board descriptions are best left to physical/layout
extraction descriptions (EDIF 4 0 0 calls out IBIS models).
Some highlights of Stephen's presentation are given. Bird 36.d defines
interconnect boundaries. In general [Application Info] is used for
connectors. The keyword arguments provide critical information that the
connector vendors feel is needed such as the rise time (bandwidth?) for which
the model valid. [Number of Pins] used for boards, unmated connectors and
such. [Number of Pairs] supports connectors that may eventually use a matrix
description. The BIRD is ambiguous about general named nodes and available
interconnections, but this is being fixed. It does make clear that if the
length is specified as greater than zero, then the element is to be assumed to
be distributed.
The coupling description and formatting issue will apply for connectors only,
not for general boards. The basic approach considered is to use cascaded,
named matrices in some format to be determined. One problem and question
is data reduction: Do you really want to describe fully a 200 pin, 4 row
connector? Another problem is accuracy. The challenge is to agree on what
the data represents and how to process it.
The mated model includes both male and female pins connected to form one
model. The unmated model represents only one of the connector components
when it is disconnected.
Discussion and debate followed concerning what is an acceptable way to
specify a coupling matrix for connectors. One consensus (?) was that such a
matrix formulation does exist, and the syntax needs to be agreed upon.
D.C. Sessions was concerned that there is no definition for the local
ground on a SIMM for local ground bounce analysis.
OTHER ITEMS AND GENERAL DISCUSSION - Syed Huq
Next meeting will be on Friday, February 14. The topic of what needs
to be done for Version 3.0 needs to be discussed.
Model verification signatures in IBIS models to document passing certain
validation tests was suggested. One response is that it is the responsibility
of the EDA companies to service their customers.
Actel asked to make the "[SOURCE]" keyword required so that all models can
be traced. However, there was opposition since there is no way to enforce
such a requirement.
NEXT MEETING:
The next meeting is on Friday, February 14, 1996, 8:00 A.M. to 9:55 A.M.
BIRD40 is scheduled for a vote along with a discussion on what needs to
be done for Version 3.0.
==============================================================================
NOTES
IBIS CHAIR: Bob Ross (503) 603-2523, Fax (503) 639-3469
bob@icx.com
Modeling Engineer, Interconnectix
10220 SW Nimbus Ave, K4, Portland, OR 97223
VICE CHAIR: Syed Huq (408) 721-4874, Fax: (408) 721-4785
huq@rockie.nsc.com
Staff Applications Engineer, National Semiconductor, M/S A-2595
2900 Semiconductor Drive, Santa Clara, CA 95052
LIBRARIAN: Jon Powell (805) 988-8250, Fax: (805) 988-8259
jonp@qdt.com
Transmission-Line Products Manager, Quad Design
1385 Del Norte Rd., Camarillo, CA 93010
SECRETARY: Vacant
This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.
The following e-mail addresses are used:
ibis-request@vhdl.org
To join, change, or drop from either the IBIS Open Forum Reflector
(ibis@vhdl.org), the IBIS Users' Group Reflector (ibis-users@vhdl.org)
or both. State your request.
ibis-info@vhdl.org
To obtain general information about IBIS, to ask specific questions
for individual response, and to inquire about joining the EIA-IBIS
Open Forum as a full Member.
ibis@vhdl.org
To send a message to the general IBIS Open Forum Reflector. This
is used mostly for IBIS Standardization business and future IBIS
technical enhancements.
ibis-users@vhdl.org
To send a message to the IBIS Users' Group Reflector. This is
used mostly for IBIS clarification, current modeling issues, and
general user concerns.
ibischk-bug@vhdl.org
To report ibischk2 parser bugs. The Bug Report Form Resides on
vhdl.org in /pub/ibis/bugs/bugform.txt along with reported bugs.
Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:
Check the pub/ibis directory on vhdl.org for more information on previous
discussions and results. You can get on via ftp anonymous, "guest" login from
telnet or dial-in (415-335-0110), or send an e-mail request to the automatic
archive server, archive@vhdl.org.
"IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for
use at trade shows.
==============================================================================
Received on Wed Feb 5 16:50:17 1997
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