Re: BIRD #61 -- Characterization of Receivers

Matthew Flora wrote:
>
> D. C.,
>
> > > > | An example table showing how receiver delay varies vs. overdrive.
> > > > | Note the use of the reserved word INF.
> > > > |
> > > > [Receiver Delay]
> > > > Start_point = 0.8v
> > > > Slope = 1v/1ns
> > > > End_point TABLE
> > > > |variable typ min max
> > > > 1.4 INF 7.0ns INF
> > > > 1.5 INF 5.0ns INF
> > > > 1.51 INF 3.0ns 10.0ns
> > > > 1.53 7.0ns 0.0ns 7.0ns
> > > > 1.55 2.0ns 0.0ns 1.0ns
> > > > 1.6 0.0ns 0.0ns 0.0ns
> > > > 1.7 0.0ns 0.0ns 0.0ns
> > > > 2.0 0.0ns 0.0ns 0.0ns
> > > > 2.1 0.1ns 0.1ns 0.1ns
> > > > 2.5 -0.2ns -0.1ns -0.5ns
> > >
> > > Often, interpolation/extrapolation is used when trying to look up values in
> > > tables. When INF appears in the table, doesn't it present a discontinuity in
> > > the data? One of the examples given showed a delay delta of 7.0ns at 1.53V
> > > and INF at 1.51V. What would the delta delay be at 1.52V? Where is the elbow
> > > in the curve? Is this simply a case of the table not having enough data
> > > points?
> >
> > I don't see how you could use the data from the tables directly, thus
> > interpolation is irrelevant.
>
> I thought we are supposed to use the delay deltas in the table to adjust the
> receiver's propagation delay. So using the example above (from the text of
> the BIRD), if the rising edge at the buffer's input rises to a final voltage
> of 1.55v, then Tco must be adjusted by 2.0ns. Correct?

Yup, although it could be Tsu as readily.

> However, if the rising edge at the buffer's input rises to a final voltage
> of 1.54v, then Tco must be adjusted by a value interpolated between 7.0ns at
> 1.53v and 2.0ns at 1.55v. Correct?

One would expect so. Then again, in The Real World (tm) input waveforms
are most unlikely indeed to slew neatly to 1.54 volts and then come to a
screeching halt at exactly that point, so the question is somewhat academic.
It is more appropriate to say that a simulator should respond to that
highly-unlikely stimulus with a value between 2000ps and 7000ps.

Given the same IBIS models with identical VT and IV tables, the same PWB
database, etc. users get different answers from Hyperlynx' simulators,
Interconnectix' simulators, Quad's simulators, Veribest's simulators, and
so forth. That charming fact allows you as programmers to have fun on the
job, your employers as vendors to differentiate their products and us as
an industry to evolve our tools by selecting superior algorithms.

Similarly, you can all come up with different interpolators. Please do.
May the best algorithm win.

> Great. Now suppose the rising edge at the buffer's input rises to a final
> voltage of 1.52v. Will the output switch? If so, what adjustment must be
> made to Tco?
>
> I believe the BIRD needs to spell this out.

On the contrary, doing so would cast the answer into stone when there's no
particular reason to suspect that it's even remotely right, much less optimal.
Just as IBIS doesn't specify an algorithm for interpolating output impedance
during transitions, it shouldn't specify an algorithm for predicting input
delays.

IBIS provides measurement points. YOU provide algorithms.
C'mon, Matt! You don't want us to hog all the fun now, do you?

-- 
D. C. Sessions
dc.sessions@vlsi.com