RE: IBIS BIRD71 - Timing Test Loads in [Model Spec] to Support PC I & PCI-X

Hi Andy:

  I agree that a testing a model with something other than a simple RC is
necessary to test the goodness of a model. I wish more folks would validate
their models with realistic transmission line type loads before releasing
them. However, the purpose of the timing test load is not to test a buffers
response in an environment with reflections, etc. -- it's to measure Tco.
For that, the timing test load should be something that produces a clean,
full-switching edge at the nominal impedance of the intended application. I
think that is what Chris was getting at, and I tend to agree.

  Regards,
  Stephen Peters
  Intel Corp.

-----Original Message-----
From: Ingraham, Andrew [mailto:Andrew.Ingraham@compaq.com]
Sent: Friday, May 11, 2001 9:06 AM
To: 'ibis@eda.org'
Subject: RE: IBIS BIRD71 - Timing Test Loads in [Model Spec] to Support
PC I & PCI-X

> I don't think the IBIS specification should allow these test
> loads. It is a mis-understanding of the purpose of these
> test loads that results in these abuses. IBIS should lead
> by explaining to the community the real purpose of test
> loads and why it is important.
 
I haven't been paying full attention lately (too much stuff going on!), but
thought I'd chime in at this point.

In digital logic, most real loads look like unterminated transmission lines,
with some capacitance sprinkled in. The old lumped C or R-C load right on
the DUT pin is unrepresentative, and may be inadequate as a test load.

That is, in fact, why PCI 2.1 (not PCI-X, by the way) changed from the
ancient 50pF test load, to the two 25 ohm loads (for 3.3V PCI parts), each
representing a pair of 50 ohm traces in parallel; one case with the lines
previously in the low state, the other in the high state. This test load
emulates infinitely-long transmission lines, which is somewhat unrealistic
(but more representative than the lumped load).

Not only that, but there are times when a few nanoseconds of transmission
line, is a partciularly useful "test" load, such as when comparing
simulations of an IBIS model to a SPICE model. And it's a good, quick way
to visually see how a part behaves when its output "rattles around," quickly
exercising how the output transistors both source and sink current (as the
outputs go beyond the rails), as well as ESD clamping, reflection
coefficient, die capacitance, and package impedance. You can reveal a lot
about a part ... or its model ... in one quick test, which the old lumped
R-C model can never show.

Regards,
Andy

 
Received on Fri May 11 10:01:14 2001