Re: Clock limitations on IBIS simulation.


Subject: Re: Clock limitations on IBIS simulation.
From: Gregory R Edlund (gedlund@us.ibm.com)
Date: Tue Jan 08 2002 - 06:39:00 PST


Dan,

In my opinion, the general answer to your question is:

If the behavioral model which the simulator employs represents the
electrical behavior of the I/O circuit AND if the person who extracted the
IBIS data understood the behavioral model and the I/O circuit, then the I/O
buffer should not be the limiting factor in the accuracy of a 1 Gb/s+
simulation.

These are rather weighty conditions. They imply you can't simply run
s2ibis on a SPICE model and then go off and simulate. This is especially
true with very high bit rate applications. The person who is doing the
modeling work really needs to understand the inner workings of the circuit
and how the behavioral model represents the circuit. The biggest factor is
whether or not the circuit designer used any special techniques, such as
edge rate control. Unfortunately, it's not simple enough to apply a rule
of thumb. I've seen 100 MHz behavioral simulations whose results I didn't
believe because the IBIS data and the behavioral model didn't represent the
actual circuit.

Greg Edlund
Electronic Packaging & Integration
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com

                                                                                                                                
                      Dan
                      Aleksandrowicz To: ibis@eda.org
                      <dan@galileo.co.i cc:
                      l> Subject: Clock limitations on IBIS simulation.
                      Sent by:
                      owner-ibis@eda.or
                      g
                                                                                                                                
                                                                                                                                
                      01/08/02 02:53 AM
                                                                                                                                
                                                                                                                                

Hi guys.

I know this question is as old as IBIS itself, but, it still rising
again.

At what clock speeds, and yes I mean DDR signals, is IBIS not
accurate to a intolerable degree ?

I know that the DC sweep analysis is clock independent, and
that the wave form reflects the actual switching of the pad.
Therefor, I believe the answer is more tool dependent.

Is the above assumption is true ? And please I am not looking
into tool compression. But, into the theoretical aspects of high
speed analysis in 1G and beyond.

Please comment - thanks.

    Danny Aleksandrowicz

#### dan.vcf has been removed from this note on January 08 2002 by Gregory
R Edlund



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