Subject: [IBIS] BIRD75.6 - Multi-Lingual Model Support - Quite LONG
From: Ross, Bob (bob_ross@mentorg.com)
Date: Fri Oct 18 2002 - 20:35:04 PDT
To IBIS Commitee:
BIRD75.6 is issued in response to more comments on BIRD75.5, mostly
from Michael Mirmak and Arpad Muranyi. The specific responses
were sent separately. In general, thank you for helping to clarify
some difficult technical areas. In several cases reasonable
alternatives were given and technically possible, but the reasons
for choosing the alternatives given in the document were presented.
Some of these choice will be subject to more debate.
These are documented with |*6 lines.
BIRD75.6 and BIRD77.1 should be considered together.
Bob Ross
Mentor Graphics
******************************************************************************
******************************************************************************
BIRD ID#: 75.6
ISSUE TITLE: Multi-Lingual Model Support
REQUESTER: Bob Ross, Mentor Graphics
DATE SUBMITTED: 3/29/02, 5/3/02, 7/15/02, 8/14/02, 9/11/02, 9/27/02, 10/18/02
DATE ACCEPTED BY IBIS OPEN FORUM: Pending
******************************************************************************
******************************************************************************
STATEMENT OF THE ISSUE:
A rapid solution is needed for complex buffer modeling beyond what IBIS
currently supports and for more complex die interconnect circuitry. The
IBIS specifications already has too many keywords to support additional
expansion. The process of developing a new specification is turning out
to be more time-consuming than anticipated.
******************************************************************************
STATEMENT OF THE RESOLVED SPECIFICATIONS:
Multi-lingual model support within IBIS can leverage publicly accepted and
standardized language implementations such as SPICE, VHDL-AMS, Verilog-AMS,
etc. to support extended buffer behavior and extended interconnect
descriptions. This proposal still uses much of IBIS directly for pinout,
package, specification, and information content and proposes linking to
external code for an additional method to simulate electrical performance
and report parameters.
This is all covered in a new Section 6b. Originally the keywords were to
be blended in the mainline Specification, but there were enough changes
and interactions to justify a new Section 6b similar to the Add Submodel
Description section.
|=============================================================================
|=============================================================================
|
| Section 6b
|
| M U L T I - L I N G U A L M O D E L D E S C R I P T I O N
|
|=============================================================================
|=============================================================================
|
| Multi-lingual support within IBIS is provided within .ibs files to allow
| extended descriptions of buffers and internal die interconnect circuitry
| that currently can be described using other languages and formats. These
| languages include SPICE, VHDL-AMS and Verilog-AMS.
|
| The extensions use the existing .ibs file format. They consist of the
| following keywords:
|
| [External Model], [End External Model] - Extended model description
| [External Circuit], [End External Circuit] - Circuitry on the die
| [Node Declarations], [End Node Declarations] - Interconnect nodes
| [Circuit Call], [End Circuit Call] - Connection description
|
| EXTERNAL LANGUAGES:
|
|** IBIS Files can reference files in any or all of the above external
|** languages to add simulation information to the [Component] or [Model]
|** keywords.
|
| The allowed languages are arguments for the Language subparameter:
|
| "SPICE" means SPICE 3, Version 3F5 developed by the University of California
| at Berkeley, California. Many vendor specific EDA tools are compatible with
| most or all of this version.
|
| "VHDL-AMS" means "IEEE Standard VHDL Analog and Mixed-Signal Extensions",
| approved 18 March 1999 by the IEEE-SA Standards Board and designated
| IEEE Std 1076.1-1999.
|
| "Verilog-AMS" means Analog and Mixed-Signal Extensions to Verilog-HDL as
| documented in the Verilog-AMS Language Reference, Version 2.0. This
|*6 document is maintained by Accellera (formerly Open Verilog
|*6 International), an independent organization. Verilog-AMS is a superset
|*6 that includes and supersedes Verilog-A and includes the Verilog Hardware
|*6 Description Language IEEE 1364-2001.
|
| In addition the "IEEE Standard Multivalue Logic System for VHDL Model
| Interoperability (Std_logic_1164)" designated IEEE Std 1164-1993 is required
| to promote common digital data types.
|
|**** An optional method of defining and passing parameters is proposed
|**** that supports both VHDL-AMS and Verilog-AMS. It will also work with
|**** some common versions of SPICE. However, these may be for special case
|**** analysis outside of SPICE Version 3F5.
|**** Remove this older paragraph-------:
|** Each of these languages have methods to pass local or global parameters
|** such
| as temperature, scaling, initial conditions, values, etc. into the portion
| of code that is being simulated. This support will continue to be done
|** within the externally referenced files.
|**** End of removed paragraph-------.
|
| REFERENCE DIAGRAMS:
|
| The details of the keywords are described later. For reference, the
| external model descriptions apply to but are not limited to the following
| diagrams:
|
| D_enable ___
| |
| |\
| D_drive____| \_______A_signal
| | / |
| |/ /| |
| D_receive____/ |__|
| \ |
| \|
|
|** The electrical terminals of each model will be referred to as ports.
| By convention, digital electrical ports are denoted by D_* and analog
| electrical ports are denoted by A_*. These prefixes are not required. The
| port names are used to describe interconnections within the IBIS file. The
| terminal names in the actual external models might differ from the port name
| assignment.
|
| Another reference diagram shows additional ports for power and other
|* connections. Except for <another name> ports, the names below are on the
| reserved port name list discussed later and relate to existing IBIS
| conventions.
|
| +---------+
| D_enable---| |---A_puref
| ||\ |---A_pcref
| D_drive----|| >----+-----A_signal
| ||/ /| | |---A_gcref
| D_receive--| < |--+ |---A_pdref
| | \| |---A_gnd
| | |---A_extref
| +--+---+--+
| | |
| D_<another name> ---+ +------A_<another name>
|
| A diagram below shows I/O Buffers connected directly to the die pad
| interface side of the package model. The top buffer shows some power pin
| connections and the bottom buffer shows only the signal connection with
| actual power supply values documented internally as in existing IBIS models.
| Either of these buffers can be an existing IBIS model or an [External Model]
| referenced in another file.
|
| _________________
| Die Nodes |
| |
| +---------+ |
| | |---*|
| ||\ |---*|
| || >----+-----*|
| ||/ /| | |---*|
| | < |--+ |---*|
| | \| | |
| +---------+ |
| |
| |
| Internal |
| Supplies |
| +---------+ |
| | | |
| ||\ | |
| || >----+-----*|
| ||/ /| | | |
| | < |--+ | |
| | \| | |
| +---------+ |
| |
|
|***** The [External Circuit] keyword can be used for any type of passive or
|***** active circuit positioned on the die, with or without connecting it
|***** to a [Model]. When the [External Circuit] is used by itself, the
|***** user or EDA tool must control how it is invoked. For example, an
|***** [External Circuit] keyword could be used to describe an operational
|***** amplifier or filter, and both could be invoked through connections
|*6 to other circuitry.
|*6
|*6 The electrical terminals of each external circuit will be referred to
|*6 as ports (similar to each model). Connections points on the die will
|*6 be referred to as nodes. The following description illustrates using the
|***** [External Circuit] keyword used with a [Model] to add interconnect
|***** circuit detail on the die.
|*****
| The [External Circuit] keyword is used to describe paths that can connect
| some or all of a [Model] to the 'Die Nodes' as shown in the diagram below.
| The connections between [Model] and [External Circuit]s are always through
| nodes. 'Internal Nodes' are shown for some connections and need to be
| declared. The diagram shows 'Die Nodes' designated by corresponding pin
| numbers, and 'Internal Nodes' by alpha characters. This diagram is used to
| illustrate the new keywords discussed later.
|
|*** This diagram is updated ***
|
| _____________________________________________
| Internal Nodes Die Nodes |
| External Circuit |
| +---------+ +--------------------+ |
| | A |--(a)--|vcca1 BUS vcc|---*| 10 Vcc
| ||\ |--(b)--|vcca2 | |
| || >----+----(c)--|int_ioa io1|---*| 1 Buffer A
| ||/ /| | |--(d)--|vssa1 | |
| | < |--+ |--(e)--|vssa2 gnd|---*| 11 GND
| | \| | | | |
| +---------+ | | |
| | | |
| +---------+ | | |
| | B |--(f)--|vccb1 | |
| ||\ |--(g)--|vccb2 BUS_SPI | |
| || >----+----(h)--|int_iob io2|---*| 2 Buffer B
| ||/ /| | |--(i)--|vssb1 BUS_VHD | |
| | < |--+ |--(j)--|vssb2 | |
| | \| | | BUS_V | |
| +----+----+ +--------------------+ |
| | |
| | Analog Buffer Control |
| +-------------------------------------*| 3 Control Resistor
| | or Voltage
|
|
|** Buffers A and B are shown connected through BUS block to the numbered die
|***** node
| connections. Buffer B has an additional buffer strength connection set
| by an external resistor or voltage. Internal nodes shown as characters
| (a) - (j) in the diagram must have names that are different from die node
| names.
|
| The [Node Declarations] and [Circuit Call] keywords presented later connect
| ports of [External Model]s or [External Circuit]s to internal or die nodes.
| An [External Circuit] or portions of it can also be connected to another
| [External Circuit] through internal nodes.
|
| KEYWORD DEFINITIONS:
|
| The [External Model] keyword is positioned within a [Model] keyword for
| which the [External Model] is used.
|
|=============================================================================
| Keyword: [External Model], [End External Model]
| Required: No
| Description: Used to reference an external file for a more detailed buffer
| description.
|**** Sub-Params: Language, Corner, Parameters, Ports, D_to_A, A_to_D
|**Usage Rules: If used, the keyword [External Model] keyword must appear
|** only once for each
|*6 [Model] keyword. It is positioned with the [Model keyword.
| It is not permitted under the [Submodel]
| keyword.
|
| Language:
| Accepts "SPICE", "VHDL-AMS", or "Verilog-AMS". The Language
| subparameter is required and can appear only once.
|
| Corner:
| Three entries follow the Corner subparameter on each line:
|
| corner_name file_name circuit_name
|
| The corner_name entry is "Typ", "Min", or "Max". The
| file_name entry points to the referenced file in the same
| directory as the .ibs file.
|
| The circuit_name entry provides the name of the circuit within
|** the referenced file to be simulated by the EDA tool. For
|** SPICE
| files, this is normally a ".subckt" name. For VHDL-AMS files,
| this is normally an "entity", "architecture" name pair with
| the architecture name enclosed in parenthesis. For
| Verilog-AMS files, this is normally a "module" name.
|
| Up to three Corner lines are permitted. A "Typ" line is
| required and shall be used for any missing corner ("Min" or
| "Max").
|
| No character limits, case-sensitivity limits or extension
| conventions are required nor enforced for file_name and
| circuit_name entries. However, the total number of characters
| in each Corner line must comply with the Section 3 limits.
|** Furthermore, lower-case file_name entries are recommended to
|** avoid possible conflicts with file naming conventions in
|** different operating systems. Case-sensitive differences
|** between otherwise identical file_name entries or circuit_name
|** entries should be avoided. Several target languages do not
|** support case-sensitive distinctions.
|
|**** Parameters:
|**** Lists names of parameters that can be passed into an external
|**** model. Each Parameters assignment is by exact reference to
|**** its name in the external model language. The list of
|**** Parameters can be presented over several lines by using the
|**** Parameters subparameter for each line. The Parameters
|**** subparameter is optional, and the external model must operate
|**** with default settings without any additional parameter
|**** assignments.
|****
|**** Parameter passing is not supported in (Berkeley) SPICE and
| is therefore
|**** not part of the standardized support in this document.
|**** However, several vendor-specific versions of SPICE pass
|**** parameters using ".param" statements in the file. VHDL-AMS
|**** parameters are supported using "generic" names, and
|**** Verilog-AMS parameters area supported using "parameter" names.
|****
|**** The parameter numerical and string formats must follow the
|**** external language format rules for strings, numerical formats,
|***** multipliers, and units.
|****
| Ports:
| Gives port names to the terminals as "ports" that are used to
| connect the external model. The port assignment is by
| position, and the port names do not have to match exactly the
| terminal names of the external model. A list of pre-defined
| port names is presented later. The list of port names can be
| presented over several lines by using the Ports subparameter
| for each line.
|
| D_to_A, A_to_D:
| Defines all digital to analog and analog to digital electrical
| interface adapters needed to interface with the digital
|** interface of referenced models. While the IBIS format assumes
| that the EDA tool itself describes and controls how and when
| the IBIS model transitions occur, some external code needs
| explicit control circuitry to be executed. For example,
| logical states control implied in IBIS requires actual input
| voltage stimuli (such as a voltage ramp input) to simulate in
| SPICE.
|
| The D_to_A subparameter is used to convert a digital stimulus
|* ('0' and '1') into an analog voltage ramp, if needed. The
|* D_to_A subparameter is followed by the following entries:
|
| d_port port1 port2 vlow vhigh trise tfall
|
|** As shown in the reference diagrams above, the d_port entry is
|** the digital port name. This entry is used
| for reserved port names: D_drive, D_enable and D_switch. The
| port1 and port2 entries name the analog ports across which
|** voltages are specified. These ports must also be named by
| the Ports subparameter. The vlow and vhigh entries are 0
| percent and 100 percent voltages where the vhigh value is
| greater than the vlow value. The trise and tfall entries must
| be positive and give the input ramp rise and fall times
| defined between 0 and 100 percent.
|
| The stimulus is applied across port1 and port2. Normally
| port1 is the input and port2 is the reference. However, for
| an opposite polarity stimulus, port1 can be connected to a
|***** voltage reference and port2 can serve as the input.
|
| The A_to_D subparameter is used to generate a digital state
| ('0', '1', or 'X') based on detecting analog voltages. The
| A_to_D subparameter is followed by the following entries:
|
| d_port port1 port2 vlow vhigh
|
|** The d_port entry refers to the digital port name and is used
|** for the
|*** reserved port name: D_receive. The voltage measurements are
| taken from the port1 entry with respect to the port2 entry.
|** These ports must also be named by the Ports subparameter.
| The vlow and vhigh entries are the low and high threshold
| voltage values. The reported digital state will be '0' if the
| measured voltage is lower than the vlow value, '1' if above
| the vhigh value, and 'X' otherwise.
|
|** True differential buffers discussed later use the A_to_D
|*** subparameter for D_receive. In a true differential external
| model, port1 and port2 are the two differential ports, often
| with reserved names A_signal_pos and A_signal_neg. The
| [Diff Pin]
| subparameter vdiff would be mapped as follows: -vdiff value
| for vlow, and the +vdiff value for vhigh. The reported logic
| states produced by the A_to_D conversion follow the same rules
|** as for single-ended buffers. The [Diff Pin] keyword is
|** required.
|
|** Differential buffers composed of individual, single-ended
|** buffers and described by the [Diff Pin] keyword have an
|** implicit A_to_D connection. The reserved signal name A_signal
|** is required for each I/O port of the
| [External Model]. The port1 connection is the A_signal port
| of the Non-inverting model, and the port2 connection is the
| A_signal port of the Inverting model. If an adapter needs to
| be configured, its vhigh takes the +vdiff value, and vlow
|** takes the -vdiff value. This is illustrated later.
|
| Other Notes: The [External Model] keyword overrides all other keywords
|***** and subparameters that describe electrical behavior, whether
|***** or not they are required below. This
| includes [Add Submodel], [Driver Schedule] and the C_comp
| subparameter and all other keywords under [Model] except
| [Model Spec]. [External Model] is not permitted under the
| [Submodel] keyword. Additional permitted keywords for the
|*** Version 4.0 of IBIS are listed in the Keyword Interaction
| Limits section below.
|***
|*** When [External Model] is used, only the following keywords
|*** and subparameters are required:
|***
|*** Model_type
|*** Vinh and Vinl according to the existing rules
|*** C_comp and/or C_comp_* according to the exisitng rules
|*** [Voltage Range] and/or [Pullup Reference], [Pulldown
|*** Reference], [Power Clamp Reference], [Gnd Clamp
|*** Reference] according to the existing rules
|**** [Ramp] according to existing rules for I/O*, 3-state*,
|**** Output*, and Open* model types.
|***
|*** This requirement supports simple rule checking even if a
|*** particular keyword or subparameter is not needed or is
|**** overridden by the [External Model] reference. The [Ramp]
|**** keyword is used by some EDA tools to estimate the pulse width
|**** for timing analysis.
|
| If other keywords exist under [Model], they must form a
|* complete set to comply with IBIS syntax rules as if the
|** [External Model] keyword were not present. The other keywords
|** can be
|* used for documentation or as a default mode of operation
|*6 should the [External Model] keyword and its subparameters be
|** be deleted or not be supported.
|-----------------------------------------------------------------------------
| SPICE Example:
|
[Model] B
Model_type I/O
|
| ... Other model subparameters including C_comp.
|
[External Model]
Language SPICE
|
| Corner corner_name file_name circuit_name (.subckt name)
Corner Typ buffer_typ.spi buffer_io_typ
Corner Min buffer_min.spi buffer_io_min
Corner Max buffer_max.spi buffer_io_max
|
|**** Parameters - Not supported in SPICE
|
| Ports List of port names (in same order as in SPICE)
Ports A_signal int_in int_en int_out A_control
Ports A_puref A_pdref A_pcref A_gcref
|
| D_to_A d_port port1 port2 vlow vhigh trise tfall
D_to_A D_drive int_in A_gcref 0.0 3.3 0.5n 0.3n
D_to_A D_enable int_en A_gcref 0.0 3.3 0.5n 0.3n
|
| A_to_D d_port port1 port2 vlow vhigh
A_to_D D_receive int_out A_gcref 0.8 2.0
|
[End External Model]
|
| VHDL-AMS Example:
|
[External Model]
Language VHDL-AMS
|
| Corner corner_name file_name circuit_name entity(architecture)
Corner Typ buffer_typ.vhd buffer(buffer_io_typ)
Corner Min buffer_min.vhd buffer(buffer_io_min)
Corner Max buffer_max.vhd buffer(buffer_io_max)
|
|**** Add this to the example-----
| Parameters List of parameters
Parameters delay rate
Parameters preemphasis
|**** End of addtion------
|
| Ports List of port names (in same order as in VHDL-AMS)
Ports A_signal A_puref A_pdref A_pcref A_gcref A_control
Ports D_drive D_enable D_receive
|
[End External Model]
|
| Verilog-AMS Example:
|
[External Model]
Language Verilog-AMS
|
| Corner corner_name file_name circuit_name (module)
Corner Typ buffer_typ.v buffer_io_typ
Corner Min buffer_min.v buffer_io_min
Corner Max buffer_max.v buffer_io_max
|
|**** Add this to the example-----
| Parameters List of parameters
Parameters delay rate
Parameters preemphasis
|**** End of addtion------
|
| Ports List of port names (in same order as in Verilog-AMS)
Ports A_signal A_puref A_pdref A_pcref A_gcref A_control
Ports D_drive D_enable D_receive
|
[End External Model]
|
|=============================================================================
|
|** The [External Circuit] keyword and contents can be placed anywhere in the
|** file, outside of any [Component] keyword group or [Model] keyword group
|** in a similar manner that the [Model] keyword itself can be placed within
|*** a file. The electrical terminals
|** of an [External Circuit] keyword are referred to as ports.
|
|=============================================================================
| Keyword: [External Circuit], [End External Circuit]
| Required: No
| Description: Used to reference an external code file for more detailed
|***** die interconnect description or for any other application.
|**** Sub-Params: Language, Corner, Parameters, Ports
| Usage Rules: Each [External Circuit] keyword is followed by a unique name
|** that differs from any name used for any [Model] or [Submodel]
|** keyword. The [External Circuit] name is referred to as
| 'Ext_name', and a [Model] name is referred to as 'Model_name'
|
|** The [External Circuit] keyword can appear multiple times. It
| is not scoped by any other keyword.
|
|** Each [External Circuit] keyword is referenced by one or more
|** [Circuit Call] keywords discussed later. (The [Circuit Call]
|** keyword can also be used to reference a [Model] keyword.)
|
| Language:
| Accepts "SPICE", "VHDL-AMS", or "Verilog-AMS". The Language
| subparameter is required and can appear only once.
|
| Corner:
| Three entries follow the Corner subparameter on each line:
|
| corner_name, file_name and circuit_name
|
| The corner_name entry is "Typ", "Min", or "Max". The
| file_name entry points to the referenced file in the same
| directory as the .ibs file.
|
| The circuit_name entry provides the name of the circuit within
|** the referenced file to be simulated by the EDA tool. For
|** SPICE
| files, this is normally a ".subckt" name. For VHDL-AMS files,
| this is normally an "entity", "architecture" name pair with
| the architecture name enclosed in parenthesis. For
| Verilog-AMS files, this is normally a "module" name.
|
| Up to three Corner lines are permitted. A "Typ" line is
| required and shall be used for any missing corner ("Min" or
| "Max").
|
| No character limits, case-sensitivity limits or extension
| conventions are required nor enforced for file_name and
| circuit_name entries. However, the total number of characters
| in each Corner line must comply with the Section 3 limits.
|** Furthermore, lower-case file_name entries are recommended to
|** avoid possible conflicts with file naming conventions in
|** different operating systems. Case-sensitive differences
|** between otherwise identical file_name entries or circuit_name
|** entries should be avoided. Several target languages do not
|** support case-sensitive distinctions.
|
|**** Parameters:
|**** Lists names of parameters that can be passed into an external
|**** circuit. Each Parameters assignment is by exact reference to
|**** its name in the external circuit language. The list of
|**** Parameters can be presented over several lines by using the
|**** Parameters subparameter for each line. The Parameters
|**** subparameter is optional, and the external circuit must
|**** operate with default settings without any additional parameter
|**** assignments.
|****
|***** Parameter passing is not supported in (Berkeley) SPICE and is
|**** therefore
|**** not part of the standardized support in this document.
|**** However, several vendor-specific versions of SPICE pass
|**** parameters using ".param" statements in the file. VHDL-AMS
|**** parameters are supported using "generic" names, and
|**** Verilog-AMS parameters area supported using "parameter" names.
|****
|**** The parameter numerical and string formats must follow the
|**** external language format rules for strings, numerical formats,
|***** multipliers, and units.
|****
| Ports:
| Gives port names to the terminals as "ports" that are used to
| connect the external circuit. The port assignment is by
| position, and the port names do not have to match exactly the
| terminal names of the external circuit. The list of port
| names can be presented over several lines by using the Ports
|*6 subparameter for each line. Some reserved port names given
|*6 later apply only to models, and not to external circuits.
|
| Other Notes: Certain other required and optional keywords under
|* [Component] can conflict with [External Circuit]. For
|* example, the optional [Pin Mapping] keyword might provide
|* different information. Other conflicting keywords are noted
|* in the Keyword Interaction Limits section below.
|-----------------------------------------------------------------------------
| SPICE Example:
|
[External Circuit] BUS_SPI
Language SPICE
|
| Corner corner_name file_name circuit_name (.subckt name)
Corner Typ bus_typ.spi Bus_typ
Corner Min bus_min.spi Bus_min
Corner Max bus_max.spi Bus_max
|
|**** Parameters - Not supported in SPICE
|
| Ports are in same order as defined in SPICE
Ports vcc gnd io1 io2
Ports int_ioa vcca1 vcca2 vssa1 vssa2
Ports int_iob vccb1 vccb2 vssb1 vssb2
|
[End External Circuit]
|
| VHDL-AMS Example:
|
[External Circuit] BUS_VHD
Language VHDL-AMS
|
| Corner corner_name file_name circuit_name entity(architecture)
Corner Typ bus.vhd Bus(Bus_typ)
Corner Min bus.vhd Bus(Bus_min)
Corner Max bus.vhd Bus(Bus_max)
|
|**** Add this to the example--------
| Parameters List of parameters
Parameters r1 l1
Parameters r2 l2 temp
|**** End of addtion--------
|
| Ports are in the same order as defined in VHDL-AMS
Ports vcc gnd io1 io2
Ports int_ioa vcca1 vcca2 vssa1 vssa2
Ports int_iob vccb1 vccb2 vssb1 vssb2
|
| Verilog-AMS Example:
|
[External Circuit] BUS_V
Language Verilog-AMS
|
| Corner corner_name file_name circuit_name (module)
Corner Typ bus.v Bus_typ
Corner Min bus.v Bus_min
Corner Max bus.v Bus_max
|
|
|**** Add this to the example------
| Parameters List of parameters
Parameters r1 l1
Parameters r2 l2 temp
|**** End of addtion------
|
| Ports are in the same order as defined in Verilog-AMS
Ports vcc gnd io1 io2
Ports int_ioa vcca1 vcca2 vssa1 vssa2
Ports int_iob vccb1 vccb2 vssb1 vssb2
|
[End External Circuit]
|
|=============================================================================
|
The following keywords are scoped by each [Component] keyword. They apply
for the specific set of pin numbers and internal nodes for only that
[Component].
|
|=============================================================================
| Keyword: [Node Declarations], [End Node Declarations]
| Required: Yes, if any internal nodes exist
| Description: Provides a list of internal nodes for interconnections.
| Usage Rules: Each [Node Declarations] keyword contains a list of internal
|*** nodes. Each node is separated by white space. The list
| may be positioned over several lines and is terminated by the
| [End Node Declarations] keyword.
|
| Only one [Node Declarations] keyword is permitted for each
| [Component] keyword. The [Node Declarations] keyword is
| part of the [Component] keyword, so all internal node
| references apply only to that [Component].
|
| If used, the [Node Declarations] keyword must appear before
| any [Circuit Call] keyword under the [Component] keyword.
|
| The internal node names within [Node Declarations] must be
| different from the pin_number names used in the [Pin] keyword.
| These pin_number names also serve as the terminals of the die
| and are also referred to as die nodes.
|-----------------------------------------------------------------------------
[Node Declarations] | Must appear before any [Circuit Call] keyword
|
a b c d e
f g h i j | Internal nodes, one or more lines permitted
|
[End Node Declarations]
|
|=============================================================================
| Keyword: [Circuit Call], [End Circuit Call]
| Required: No
| Description: Defines connections between the terminals of external circuits
| or models designated as ports and the declared internal nodes
| or the die nodes at the die interface.
| Sub-Params: Port_map, Signal_pin, Diff_signal_pins, Series_pins
| Usage Rules: Each [Circuit Call] is followed by a Model_name or Ext_name
| that references the IBIS [Model] keyword Model_name or the
| [External Circuit] Ext_name.
|
| The keyword [Circuit Call] can appear multiple times, under
| [Component], as required, and is part of the [Component]
|* keyword. Different [Circuit Call] keywords can reference the
| same Ext_name or Model_name to describe a different set of
| connections. The [Circuit Call] subparameters are required
| as described below.
|
| Port_map:
| Port_map is followed by a port name and then a node name.
| The port name must be one of the ports in the referenced
| [External Circuit] or [External Model] and must appear only
|* once. However, node names can be repeated to signify a
| connection between ports such as with a common voltage supply.
| The node name may be a die node name or an internal, declared
| node. One Port_map subparameter must exist for each of the
|*** defined ports in the [External Circuit] or [External Model].
|
| Signal_pin, Diff_signal_pins, Series_pins:
| When the [Circuit Call] keyword names a [Model] keyword,
| either Signal_pin, Diff_signal_pins or Series_pins are
| required.
|
| Signal_pin is used when the referenced model uses one I/O
| port.
| It is followed by a die node name (same as the corresponding
| pin number). Each Signal_pin name must be unique for the
| component.
|
| Diff_signal_pins is used when the referenced model is a true
| differential model (discussed later). It is followed by two
| die node names (same as the corresponding pin numbers) for the
| differential pins. These names are the non-inverting and the
| inverting die node names. The Diff_signal_pins subparameter is
| not used when the differential buffer model is created using
| the [Diff Pin] keyword and independent single-ended models.
| The Diff_signal_pins names must be unique and different from
| any
| Signal_pin name for the component.
|
| Series_pins is used when the referenced model is a Series
|** or Series_switch model (discussed later). It is followed by
| two die node names (same as the corresponding pin numbers) for
| the positive and negative pins. The polarity order matters
| only when the passive model is polarity sensitive (as with the
| the [Series Current] keyword). Many Series models can also be
| described directly using the [External Circuit] keyword.
| Series_pins names do not have to be unique and can be
| the
| same as Signal_pin or Diff_signal_pins names for the component.
|-----------------------------------------------------------------------------
| Circuit Call to model:
|
[Circuit Call] A | References the Model_name of a [Model]
|
Signal_pin 1 | Used only for calls to Models.
|
| mapping port node
Port_map A_signal c | Port to internal node connections
Port_map A_puref a
Port_map A_pdref b
Port_map A_pcref d
Port_map A_gcref e
|
[End Circuit Call]
|
[Circuit Call] B | References the Model_name of a [Model]
|
Signal_pin 2 | Used only for calls to Models.
|
| mapping port node
Port_map A_signal h
Port_map A_control 3 | Control port to die node
Port_map A_puref f
Port_map A_pdref g
Port_map A_pcref i
Port_map A_gcref j
|
[End Circuit Call]
|
| Circuit Call to die interconnect circuit:
|
[Circuit Call] BUS_SPI | References the Ext_name of an [External Circuit]
|
| mapping port node
Port_map vcc 10
Port_map gnd 11
Port_map io1 1
Port_map io2 2
Port_map vcca1 a
Port_map vcca2 b
Port_map int_ioa c
Port_map vssa1 d
Port_map vssa2 e
Port_map vccb1 f
Port_map vccb2 g
Port_map int_iob h
Port_map vssb1 i
Port_map vssb2 j
|
[End Circuit Call]
|
|=============================================================================
|
| TRUE DIFFERENTIAL MODEL:
|
|** True differential models are supported in IBIS ONLY with [External Model]
|** as
|* shown in the reference diagram:
|
| D_enable ___
| |
| |\
| D_drive____| \----+-----A_signal_pos
| | /----|--+--A_signal_neg
| |/ /| | |
| D_receive____/ |--+ |
| \ |-----+
| \|
|
|
|** The [Diff Pin] keyword is required to designate true differential models
|** under the [Component] keyword. The models referenced by each pin must
|** be the same. (This is not a requirement for differential models specified
|** from single-ended buffers.)
|**
|** Four new Model_type arguments are required under the [Model] keyword:
|**
|** I/O_diff, Output_diff, 3-state_diff, and Input_diff
|**
|** Two new differential timing test loads are permitted:
|**
|** Rref_diff, Cref_diff
|**
|** These subparameters are also available under the [Model Spec] keyword for
|** typical, minimum, and maximum column entry differences.
|**
|** These new timing test loads require both sides of the differential model
|** to be operated. They can be used with the existing timing test loads
|** Rref, Cref, and Vref. The existing timing test loads and Vmeas is used
|** if Rref_diff and Cref_diff are NOT given.
|
|** This paragraph is deleted
|* Because the model requires an [External Model] reference, the existing
|* reserved power reference names are not needed. However, this model uses
|* the same reserved port names for single-ended digital control connections.
|* The model developer will need other interfacing circuitry for the D_drive
|* and D_enable signals if differential connections are used to control the
|* model.
|** End of deletion
|
|** The digital controls D_drive and D_enable assume single-ended control
|** connections. The D_to_A adapters used for SPICE files can be set up to
|** control single-ended or true differntial terminal.
|
| The example below shows how to document
|***the A_to_D adapter when vdiff is 200 mV. Set vlow as -200 mV and vhigh as
|*** 200 mV.
|-----------------------------------------------------------------------------
| Example of True External Differential SPICE Buffer:
|
[Model] External_Diff_Buffer
Model_type I/O_diff
Rref_diff = 100
|
| ... Other model subparameters including C_comp.
|
[External Model]
Language SPICE
|
| Corner corner_name file_name circuit_name (.subckt name)
Corner Typ diffio.spi diff_io_typ
Corner Min diffio.spi diff_io_min
Corner Max diffio.spi diff_io_max
|
| Ports List of port names (in same order as in SPICE)
Ports A_signal_pos A_signal_neg int_in int_en
Ports A_puref A_pdref A_pcref A_gcref
|
| D_to_A d_port port1 port2 vlow vhigh trise tfall
D_to_A D_drive int_in A_gcref 0.0 3.3 0.5n 0.3n
D_to_A D_enable int_en A_gcref 0.0 3.3 0.5n 0.3n
|
| A_to_D d_port port1 port2 vlow vhigh
A_to_D D_receive A_signal_pos A_signal_neg -200m 200m
|
[End External Model]
|
|-----------------------------------------------------------------------------
|
| DIFFERENTIAL MODEL FROM SINGLE-ENDED BUFFERS:
|
| The method of specifing differential buffers constructed from single-ended
| models remains the same with or without using the [External Model] keyword.
| The [Diff Pin] keyword is used in all cases, with or without paths defined
| using the [External Circuit] keyword. The method requires using the
| reserved A_signal port.
|
| The reference diagram for each buffer is the same as a single-ended buffer
|** except that the two buffers provide non-inverting and inverting ports,
|** and the digitial control signals are shared between the buffers:
|
| _____D_enable ___
| | |
| | |\
| | __D_drive____| \_______A_signal (Non-inverting)
| | | | / |
| | | |/ /| |
| | | D_receive____/ |--+
| | | \ |--+
| | | |\ \| |
| | |_____________| \____|__A_signal (Inverting)
| | | /
| | |/
| |_________________|
|
| The D_receive connection is specified through the [Diff Pin] keyword, its
| pin listings and its vdiff subparameter. In addition, the tdelays may be
| inserted in the A_signal paths for relative timing skew modeling. For an
| Input* or I/O* model, each [External Model] must name an A_signal port.
| These ports are implicitly connected to the D_receive as shown in the
| reference diagram.
|
| The [Diff Pin] subparameters determine the polarity reference of D_receive
| according to the pins assigned to the [Diff Pin] and inv_pin columns.
| For example, the Signal_pin name for the [Diff Pin] column is the
| non-inverting connection, and the Signal_pin name for the inv_pin column is
| the inverting connection. The vdiff value is used to determine the
| D_receive states.
|**
|** Similar to the true differential model, two new differential timing test
|** loads are permitted:
|**
|** Rref_diff, Cref_diff
|**
|** These subparameters are also available under the [Model Spec] keyword for
|** typical, minimum, and maximum column entry differences.
|**
|** These new timing test loads require both sides of the differential model
|** to be operated. They can be used with the existing timing test loads
|** Rref, Cref, and Vref. The existing timing test loads and Vmeas are used
|** if Rref_diff and Cref_diff are NOT given.
|
| RESERVED PORT NAMES:
|
| To promote model interchangeability, the following port names are reserved
|*6 for models only (not external circu:
|
|** A_signal - I/O electrical terminal of a model
|** A_signal_pos - Non-inverting I/O electrical terminal of a differential
| model
|** A_signal_neg - Inverting I/O electrical terminal of a differential model
|
|** A_pos - Non-inverting terminal of a series model
|** A_neg - Inverting terminal of a series model
|
| D_drive - Digital drive of a buffer
| D_enable - Digital enable of a buffer
| D_receive - Digital state of a receiver
|
|** A_puref - Pullup reference voltage terminal
|** A_pcref - Power clamp reference voltage terminal
|** A_pdref - Pulldown reference voltage terminal
|** A_gcref - Ground clamp reference voltage terminal
|
|** A_extref - External reference voltage terminal, if applicable
|** A_gnd - Global reference voltage terminal, if needed, for an electrical
|** reference connection
|
| EXISTING IBIS MODEL SUPPORT:
|
| An existing IBIS model without the [External Model] can be used. The
|** reserved port names A_signal, A_pos and A_neg are assumed corresponding
|** to the appropriate Model_type since these ports
| are not defined. The [Circuit Call] keyword can be used to connect the
| model directly to the die node or through paths described by the
| [External Circuit] keyword.
|
| A_signal_pos and A_signal_neg are the reserved port names for true
| differential
| models (not supported in the existing IBIS format) and require using the
| [External Model] keyword.
|
|** REFERENCE VOLTAGES:
|
|** Existing IBIS models use the voltages given by the [Voltage Range] and/or
|** the [Pullup Reference], [Pulldown Reference], [Power Clamp Reference] and
|** [Gnd Clamp Reference] keywords. The [Pin Mapping] keyword provides a
|** method to specify which buffer is attached to which power supply or ground
|** bus.
|
|** The [Circuit Call] keyword provides an alternative way of attaching a
|** [Model] to a power supply or ground bus. This approach provides a more
|** general connection description that may include connections through
|** circuits defined by the [External Circuit] keyword. An existing IBIS
|** [Model] keyword without an [External Model] inside can be connected
|** through the predefined A_puref, A_pcref, A_pdref, A_gcref and A_gnd
|** terminals with the [Circuit Call] keyword. However, this method should
|** not be mixed with the [Pin Mapping] method because each method can provide
|** different and possibly conflicting information.
|
|****Three cases exist to connect reference voltages to an [External Model].
|****
|**** (1) No reserved port names for voltage terminals are defined in the
|**** [External Model]. The voltage references are hard-coded in the
|**** file defined by the Corner subparameter.
|****
|****The remaining two cases require that all of the voltage ports used by the
|****file must be named by the Ports subparameter:
|**
|**** (2) All ports must be connected using the [Circuit Call] keyword.
|**
|**** (3) No Ports are connected by the [Circuit Call] keyword. The reserved
|** port names for voltage terminals must be used in the Ports
|** subparameter for [External Model], and these ports are automatically
|** connected to the voltages defined under the [Voltage Range],
|** [Pullup Reference], [Pulldown Reference], [Gnd Clamp Reference],
|** and [Gnd Clamp Reference] keywords. Note, for ECL type structures,
|** only the A_puref would need to be specified.
|**
|* The reference, A_gnd, is implied in existing IBIS models and may also
| appear as a port in certain [External Model]s or [External Circuit]s. If
|** A_gnd is not connected, it shall be attached to an electrical reference,
|** usually 0 volts by the EDA tool. No error is reported for this case.
|***
|***Note, that some languages such as SPICE support global nodes (such as
|***vcc and vss) for voltages and other parameters. These global node
|***settings need to be removed if there are made variable under some
|***connection options.
|
| INTERACTION WITH THE MODEL_TYPE SUBPARAMETER OF [MODEL]:
|
| The Model_type subparameter describes the buffer. The Ports below serve as
| default Port names when only the [Model] keyword is specified without
| [External Model]. When [External Model] is specified, digital port names
| are required for digital control in a manner compatible with other models.
|
|** Model_type D_drive D_enable D_receive A_signal D_switch A_pos A_neg
|
| I/O* X X X X
| 3-state* X X X
| Output*, Open* X X
| Input X X
| Terminator X
| Series X X
| Series_switch X X X
|
|** Model_type D_drive D_enable D_receive A_signal_pos A_signal_neg
|
|** I/O_diff X X X X X
|** 3-state_diff X X X X
|** Output_diff X X X
|** Input_diff X X X
|
| Series and Series_switch devices can be described using the [External Model]
| keyword as polarity sensitive, two-terminal models. The reserved signal
| names A_pos and A_neg are assumed if such a device is defined with existing
| IBIS syntax without [External Model]. The reserved names are needed for
| connecting the model through an [External Circuit] path. The A_pos
| connection is the die node (pin) defined by the first column of the [Series
|* Pin Mapping] keyword, and the A_neg connection is to the die node (pin)
|*defined in the pin2 column. However, the A_pos and A_neg port names are not
|*required when [External Model] is used because the necessary connections are
|* made directly.
|
| Any [Circuit Call] keyword that names a [Model] for a Series_switch or
| Series device must also use Series_pins to name the corresponding die
| nodes. The Series_switch models still need to reference the die nodes to
| control the D_switch setting, where '0' is Off and '1' is On.
|
| For Series devices, an [External Circuit] keyword can be used to avoid the
| need for the Series_pins subparameter in the corresponding reference
| by [Circuit Call].
|
| COMPONENT MEASUREMENT LOCATIONS:
|
| The [Component] keyword contains the subparameters Si_location and
| Timing_location. The arguments are 'Pin' and 'Die'. The 'Pin' argument
| will continue to be interpreted as the pin side of the package model. The
|** 'Die' argument will continue to mean the die node side of the package
|** model.
|*
|* Description 2 (per IBIS Futures Group recommendation) -(remove in document)
|*
| REGISTERING MODELS:
|
| The [Pin] keyword subparameter model_name is used to register [Model]s and
| signify a direct connection to the die node. The model_name is still
| entered when a model or any part of it is connected by the [Circuit Call]
| keyword. This name must match the corresponding model_name referenced in
| the [Circuit Call] keyword for the die nodes (pins) named by Signal_pin or
|* Diff_signal_pins. The model_name reference under the [Pin] keyword is
|* redundant, but it serves to document the signal port connections of each
|* [Model] to each die node for all direct or indirect connections.
|
|-----------------------------------------------------------------------------
| Example of Registration:
|
[Pin] signal_name model_name R_pin L_pin C_pin
|
1 A A | Models A and B are connected through [External
2 B B | Circuit] and [Circuit Call] keywords
3 Control_pin NC | Control_pin connection is though [Circuit Call]
| ... | to a circuit outside of the component
10 POWER POWER
11 GND GND
| ...
|-----------------------------------------------------------------------------
|
| KEYWORD INTERACTION LIMITS:
|
| Because the set of features in this section expand connection options and
| extend functionality, some IBIS keyword limitations exist when using
| [External Model] and/or [External Circuit]. New limitations for Version 4.0
| are noted. Not all conflicting information can be checked.
|
| [Model Selector]:
| The [Model Selector] keyword should be avoided since it can reference
| another [Model] having a different set of Port names that are not
| compatible with the related [Circuit Call] keyword.
|
| [Pin Mapping]:
| The [Pin Mapping] keyword can provide conflicting information with
| [Circuit Call] and does not support the more general networks that
| [External Circuit] supports. If necessary, the [Pin Mapping] busses
| can be expressed using the [External Circuit] keyword.
|
|** The paragraph below is deleted ------:
| [Diff Pin]:
| The [Diff Pin] keyword is ignored when [External Model] used to
| configure a true differential structure since all the information is
| available in the [External Model] and the associated [Circuit Call]
|** keywords with the Diff_signal_pins subparameter.
|** End of deletion ---------
|
| [Series Pin Mapping], [Series Switch Groups]:
| The [Series Pin Mapping] keyword is ignored when [External Model] is
| used to configure a Series two-pin structure. The necessary connection
|** associations are contained in the [Circuit Call] keyword and
| Series_pins subparameter.
|
| However, Series_switch models using the [External Model] keyword still
| need the [Series Pin Mapping] keyword to define the associations with
| with die nodes (pins) and the function_table_group subparameter. The
| appropriate settings that control D_switch are then available using
| the [Series Switch Groups] keyword.
|
| It is possible to use the [External Circuit] for similar connectivity
| without needing [Series Pin Mapping] or [Series Switch Groups], but
| the switching configurations would have to be set up on a case-by-case
|* basis in each EDA tool.
|
| [Model] keywords when using [External Model]:
| Replaces all keywords under [Model] except [Model Spec], (Version 3.2)
| Replaces all new keywords under [Model] except [Receiver Thresholds],
| [External Reference] (unless using A_extref), [Test Data], and
| [Test Load]. (Version 4.0)
| Replaces C_comp subparameter. (Version 3.2)
|** Replaces the C_comp_pullup, C_comp_pulldown, C_comp_power_clamp, and
|** C_comp_gnd_clamp subparameters. (Version 4.0)
|
|=============================================================================
******************************************************************************
ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:
The IBIS-X Macro-language activity is addressing the extended model behavior
problem. However, its solution depends upon a new syntactical macro-language
which will take time to debug and implement. While a single, common
macro-language is highly desirable, An alternative, simpler, shorter term
path that leverages off industrially accepted public formats and standards
will also address the industrial needs in a very IBIS compatible manner.
Two types of languages that lend themselves to extending IBIS: SPICE and
various hardware description languages with analog/mixed signal extensions.
While either type of language can be used for all extensions, SPICE formats
are particularly strong for electrical interconnect extensions and structural
device descriptions while the hardware description languages are particularly
strong in equation handling and behavioral/logical extensions.
At this time Berkeley SPICE, VHDL-AMS and Verilog-AMS are the proposed
targeted extension languages. This is based on several desirable criteria:
Applicable to electrical circuit, device, and modeling issues
Open, publicly available format
Widely used, either directly or through emulation
Controlled under an official standardization group or independent body
Language is stable and is expected to remain downward compatible
The official IBIS list should not include vendor-specific implementations,
extensions, or deviations even if they are widely used. Vendors can deal
this issue by non-compliant IBIS extensions or interpretations.
These criteria are intended to limit the support of many language formats
(especially private de facto formats) to maximize model interoperability.
Berkeley level 3F5, VHDL-AMS and related extensions, and Verilog-AMS appear
to meet the above criteria. Verilog-AMS is still being processed for formal
IEEE standardization. So, the reference recognizes that the language call
will eventually mean the full, officially approved version.
Berkeley SPICE 3F5 is no longer readily available. However, it has served as
the basis of a number of commercial implementations that it still serves as a
SPICE baseline reference. Berkeley SPICE 2G6 could also have served as a
base, but it contains numerical node naming restrictions and other
restrictions that are not seen in practice.
External language syntax is not embedded within .ibs files because in most
tools such syntax would have to be exported into separate files in order for
the EDA tool to test and process it without syntactical errors.
BIRD75 was reviewed by the IBIS Futures Working Group, and a number of choices
already resolved are reflected in this BIRD75. Two Registration choices are
given for discussion. Description 1 supports possible future EBD style
syntactical expansion where several models can be associated with a die node
(pin). Description 2 supports existing IBIS conventions with a tight
association of a specific model_name to a pin number, even if there are added
electrical paths on the die.
BIRD75.1 has some editorial corrections. The Registration option below
is captured
|*
|* Description 1
|*
| REGISTERING MODELS:
|
| The [Pin] keyword subparameter model_name is used to register [Model]s and
| signify a direct connection to the die node. However, the model_name entry
| must be NC when a model or any part of it is connected by the [Circuit Call]
| keyword. Normally, this convention is used to distinguish direct die node
| connections from indirect die node connections that occur through paths
| given by the [External Circuit] keyword. However, NC can also be optionally
| used with [Circuit Call] even if the connections (A_signal* ports) are made
| directly to the die nodes. The [Circuit Call] keyword provides both the
| model_name and Cell_port (or Diff_cell_port) die nodes, so NC is entered
| under the [Pin] keyword to avoid redundant information.
|
|-----------------------------------------------------------------------------
| Example of Registration:
|
[Pin] signal_name model_name R_pin L_pin C_pin
|
1 A NC | Models A and B are connected through [External
2 B NC | Circuit] and [Circuit Call] keywords
3 Control_pin NC | Control_pin connection is though [Circuit Call]
| ... | to a circuit outside of the component
10 POWER POWER
11 GND GND
| ...
|-----------------------------------------------------------------------------
The futures group stated that they preferred the model name in the pin
list, even if it is redundant. BIRD75.1 documents this is Description 2.
BIRD75.2:
BIRD75.2 makes some editorial changes suggested by Arpad Muranyi and others.
Also several [Circuit Call] subparameters are renamed to better reflect the
association of a model to a particular pin (or corresponding die node):
Cell_port to Signal_pin
Diff_cell_port to Diff_signal_pins
Series_cell_port to Series_pins
BIRD75.2 also changes from BIRD75.1 the Timing_location and SI_location
"Die" specification to mean the die node side of the package model (rather
than the A_signal* location on the model. This is consistent with the
existing definition and with die measurement techniques.
More consideration is done for true differential buffers when using
[External Model]. The additions include:
Four new Model_type entries:
I/O_diff, Output_diff, Input_diff, 3-state_diff
and two new differential timing test loads:
Rref_diff, Cref_diff
These are also added to the [Model Spec] subparameter list for possible
typ/min/max variations.
The rules for the *_diff model types will be changed:
[Diff Pin] is required, not optional for true differential model
The models on each pin must be identical (not so for single-ended
constructions)
The *_diff timing test loads are used under differential conditions
The single-ended timing test loads Vref, Rref, Cref are still permitted
without the *_diff timing test loads or in combination with *_diff
And, the *_diff timing test loads can be used with single-ended
construction of differential buffers.
The predefined signals A_signal_p and A_signal_n are changed to
A_signal_pos and A_signal_neg for clarity.
These changes are made for clarity, consistency with IBIS and expansion.
Also, a case is given using the predefined reference signals where the
[External Model] can be set up with external voltages that are defined
for typ/min/max cases by the IBIS Keywords [Voltage Range] or the
[Pullup Reference], [Pulldown Reference], [Power Clamp Reference], and
[Gnd Clamp Reference] keywords.
This is added to let the existing IBIS voltage columns be used to provide
typ/min/max voltages on models under with existing IBIS controls. The
predefined port names for voltage reference terminals support this addition.
In addition, because six new subparameters are introduced as keywords
under existing IBIS, the pending IBIS Version 4.0 document needs to show
the specific subparameter additions to the [Model] and [Model Spec]
keywords. Since BIRD75.2 is already very long, a new BIRD77 will
be introduced separately to show changes in the IBIS Version 4.0
document for these existing keywords. Both BIRD75.2 and BIRD77
need to be considered together.
BIRD75.3:
As a result of the August 9, 2002 meeting and private responses, a number
of clarification improvements have been made as noted by |*** lines.
BIRD75.4:
BIRD75.4 is issued in response to the August 30, 2002 meeting comments.
The major addition was to propose as syntax for parameterization.
This is accomplished by a new subparameter "Parameters" under both
the [External Circuit] and [External Model] keywords. This would only
be supported in VHDL-AMS and Verilog-AMS since (Berkeley) SPICE does not
support a method that is used by several vendor-specific SPICEs. The
method proposes parameter values as quoted strings because there can be
spaces in some languages ("1.0 ns") and unique format conventions and
case sensitivity/insensitivity rules in others. The parameters are
required to be passed according to the formatting rules of the external
language.
Also, the methods to connect reference supplies to external models is
clarified. The [Ramp] keyword is now added to the list of required
keywords when [External Model] is present for I/O*, Output*, 3-state*
and Open* model types. While [Ramp] would not be used for buffer simulation,
it is often used in tools to get an estimate of the pulse duration for timing
tests in existing IBIS. So the [Ramp] requirement is retained.
No change was made at this time with respect to the positioning of
[External Model]. Some concerns were not addressed because I did
not fully understand the issueS.
These are documented with |**** lines.
BIRD75.5
Editorial changes are made in response to the September 20, 2002 comments
and are documented by |***** lines. These changes include clarifying that
the [External Circuit] can be used for any type of passive or active circuit
and does not have to be associated with a [Model].
BIRD75.6
More changes, suggested by Michael Mirmak and Arpad Muranyi (privately)
are made and noted by |*6 comments.
******************************************************************************
ANY OTHER BACKGROUND INFORMATION:
BIRD75 is follow up to an introductory given at the IBIS Summit Meetings
on January 28, 2002 and March 8, 2002.
BIRD77 is needed to document some new subparameters to existing IBIS
keywords for [Model] and [Model Spec].
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This archive was generated by hypermail 2b28 : Fri Oct 18 2002 - 20:47:36 PDT