Subject: RE: [IBIS] Time scale for VT plots on IBIS model.
From: Muranyi, Arpad (arpad.muranyi@intel.com)
Date: Wed Nov 13 2002 - 11:17:14 PST
Negative time would mean a non-causal system. Output before input!
I don't think our simulators can handle it...
Arpad
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-----Original Message-----
From: Beal, Weston [mailto:weston_beal@mentorg.com]
Sent: Wednesday, November 13, 2002 9:28 AM
To: 'Baumann, Hans-Gerhard'; 'ibis@eda.org'
Subject: RE: [IBIS] Time scale for VT plots on IBIS model.
Gerd,
While the IBIS specification does not explicitly prohibit time values less
than 0, I'll bet that all the simulator vendors assumed that time is always
positive. A model with negative times in the waveforms will most likely not
work.
If you want to do a full simulation of your clock tree then you'll need to
use a timing analysis tool along with your SI tool. First, you must
correctly specify the input thresholds, timing reference load, and
corresponding device propagation delay of the clock buffer. Then you can
simulate the net driving into the clock buffer, the clock buffer driving its
net and use the interconnect delays in your timing analysis that includes
the delay through the clock buffer.
This buffer delay might be negative in some cases in order to correlate with
the other simulations. Don't worry too much about negative delays of parts
of the circuit. This is a possible and logical byproduct of the way we
measure the sections of the overall circuit in different simulators. When
you add up the component propagation delays with interconnect delays, then
the sum should be positive.
So, don't put negative times in your IBIS model. Use a timing analysis tool
to augment the features of your SI tool.
Regards,
Weston
-----Original Message-----
From: Baumann, Hans-Gerhard [mailto:HGBaumann@ti.com]
Sent: Wednesday, November 13, 2002 6:52 AM
To: 'ibis@eda.org'
Subject: [IBIS] Time scale for VT plots on IBIS model.
I am working to generate IBIS models for "zero delay buffers". The main
building block is a internal PLL. One differentiation between different
products is the phase relation between input and output. Different products
have different phase.
I thought, in system simulation it might be interesting if the IBIS model
reflects the "locked phase" on its VT-tables. This however might require
that a negative start time is acceptable. I am not sure if this is OK with
current IBIS spec (working with version 3.2) or if there are plans to accept
this in future.
Any recommendation on that ?
Best Regards,
Gerd Baumann
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