Subject: [IBIS] IBIS parser bug74 update
From: Peters, Stephen (stephen.peters@intel.com)
Date: Tue Apr 01 2003 - 11:21:02 PST
Hello All:
At the last IBIS teleconference I took the action item to post additional
information from Greg Edlund on ibischk BUG74 ("Missing Timing Test Load
Warning Messages") so that this bug report could be considered at the next
teleconference. The additional information, which deals with default
assumptions for timing test loads and what combinations are required per
model type, is below. To see the entire bug report, visit the following
URL.
http://www.eda.org/pub/ibis/bugs/ibischk/bug74
<http://www.eda.org/pub/ibis/bugs/ibischk/bug74>
Regards,
Stephen Peters
Intel Corp.
********************************************
1. Implied defaults Cref=0, Vref=0, Rref=infinity
I don't think this belongs in the error message because it is tool
specific. Each tool vendor must decide on the default value of these
parameters.
2. Model_types (I/0*, Output*, 3-state*, Open*
Covered by table below.
3. Possible Rref value needed for Open*
Covered by table below.
4. Mention that [Model Spec] may contain the parameters and needs to be
part of the check, if it exists.
As I read the IBIS spec, the Vmeas subparameter defined under the
[Model Spec] keyword pertains to input timing thresholds, whereas
BUG74 pertains to output timing test loads. These are two different
things; therefore the bug fix can ignore the Vmeas subparameter when
it occurs under the [Model Spec] keyword.
Vmeas Rref/Vref
Required Required
-------- --------
Input NO NO
I/O YES NO
I/O_open_drain YES YES
I/O_open_sink YES YES
I/O_open_source YES YES
Input_ECL NO NO
I/O_ECL YES YES
Terminator NO NO
Output YES NO
3-state YES NO
Open_sink YES YES
Open_drain YES YES
Open_source YES YES
Input_ECL NO NO
Output_ECL YES YES
I/O_ECL YES YES
3-state_ECL YES YES
Series NO NO
Series_switch NO NO
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