RE: [IBIS] How we can model startup time in IBIS.

From: Akhilesh CHANDRA <akhilesh.chandra_at_.....>
Date: Mon May 14 2007 - 22:52:48 PDT
Hello Tony,

  Thanx for your reply. Initial delay is not important for SI simulations
but if it's missing in our model then it's difficult to match spice and IBIS
results also few customers  use these models for delay calculation if I
don't support this startup time then customer have only 300ps delay while in
silicon it's 3.3ns. 

Regards
Akhilesh

-----Original Message-----
From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On Behalf
Of Dunbar, Tony
Sent: Monday, May 14, 2007 10:22 PM
To: ibis@server.eda-stds.org
Subject: RE: [IBIS] How we can model startup time in IBIS.

Hi Akhilesh,

I've pondered this for a little while and all I can come up with is to ask
why is this an important or even relevant functional detail to be included
in a signal integrity simulation, presuming it is a signal integrity
simulation you are wanting to do?

An "initial delay" can be incorporated into the stimulus of some SI
simulators but that is really intended to provide for driver-to-driver skew,
whereas your brief description refers to "startup".

Regards,
Tony

-----Original Message-----
From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On Behalf
Of Akhilesh CHANDRA
Sent: Monday, May 14, 2007 4:18 AM
To: ibis@server.eda-stds.org
Cc: Akhilesh CHANDRA
Subject: [IBIS] How we can model startup time in IBIS.

 

Hello Experts,

  I am doing IBIS model of an IO operating at 800MHZ frequency. It have
startup time of 3nsec. After 3ns design gives output of 800mhz frequency. If
I model this time in waveform database of IBIS models the I have over
clocking issue and design is not work at this high frequency. Can you help
me to model this startup time. Is anyone make IBIS model of such designs.

Regards
Akhilesh


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Received on Mon May 14 22:53:47 2007

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