RE: [IBIS] How we can model startup time in IBIS.

From: Mandel, Cary <cary_mandel_at_.....>
Date: Mon May 21 2007 - 03:19:01 PDT
Akhilesh,

HyperLynx and ICX from Mentor Graphics handle "timing correction to
reference load" as well. Mentor is no longer selling XTK.

Regards,
Cary


-----Original Message-----
From: Akhilesh CHANDRA [mailto:akhilesh.chandra@st.com]
Sent: Thursday, May 17, 2007 6:06 AM
To: 'Todd Westerhoff'; ibis@eda-stds.org
Cc: Akhilesh CHANDRA
Subject: RE: [IBIS] How we can model startup time in IBIS.

 hello Todd,

  Thanx for this important info. I have one doubt.

  According to paragraph 3 "IBIS simulations are always compared to a
simulation of a "reference load", because the comparison to the standard
load simulation normalizes out the start time of the model".

  In my case cell delay is 300ps while it's startup time is 3ns. How
it's normalizes when I use standard load. 

Regards
Akhilesh

-----Original Message-----
From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On
Behalf Of Todd Westerhoff
Sent: Tuesday, May 15, 2007 6:48 PM
To: ibis@server.eda-stds.org
Subject: RE: [IBIS] How we can model startup time in IBIS.

Akhilesh,

If you or your customers are correlating simulation results in IBIS to a
transistor level equivalent, it's important to understand that "time 0"
in an IBIS model is arbitrary.  There's no guarantee that an IBIS and
transistor model simulated side by side will produce outputs at the same
time, and "shifting" the IBIS result in time to get correlation is
completely legal.

Bonnie's article made this same point.  She mentioned that a transistor
model includes the delay through the buffer, while the IBIS model
represents the output behavior but not necessarily the model's intrinsic
delay.

This is the reason IBIS simulations are always compared to a simulation
of a "reference load", because the comparison to the standard load
simulation normalizes out the start time of the model.  

If you're looking to use SI simulations to derive an interconnect delay
for plugging back into a timing analysis, you should ALWAYS be
normalizing your SI simulations to a reference load.  The startup time
of the model gets subtracted out in this case, and you should end up
with the same number for the interconnect delay whether you use the
transistor or IBIS model.  

Some would argue that transistor level simulations don't need to be
normalized; I would disagree.  It's true that you can define specific
timing and SI strategies where normalization of transistor level SI
simulations isn't required; but most people aren't running analysis
under those conditions.

Todd.

Todd Westerhoff
VP, Software Products
SiSoft
6 Clock Tower Place, Suite 250
Maynard, MA  01754
(978) 461-0449 x24
twesterh@sisoft.com
www.sisoft.com

-----Original Message-----
From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of
Akhilesh CHANDRA
Sent: Tuesday, May 15, 2007 1:53 AM
To: 'Dunbar, Tony'; ibis@eda-stds.org
Cc: Akhilesh CHANDRA
Subject: RE: [IBIS] How we can model startup time in IBIS.

Hello Tony,

  Thanx for your reply. Initial delay is not important for SI
simulations but if it's missing in our model then it's difficult to
match spice and IBIS results also few customers  use these models for
delay calculation if I don't support this startup time then customer
have only 300ps delay while in silicon it's 3.3ns. 

Regards
Akhilesh

-----Original Message-----
From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On
Behalf Of Dunbar, Tony
Sent: Monday, May 14, 2007 10:22 PM
To: ibis@server.eda-stds.org
Subject: RE: [IBIS] How we can model startup time in IBIS.

Hi Akhilesh,

I've pondered this for a little while and all I can come up with is to
ask why is this an important or even relevant functional detail to be
included in a signal integrity simulation, presuming it is a signal
integrity simulation you are wanting to do?

An "initial delay" can be incorporated into the stimulus of some SI
simulators but that is really intended to provide for driver-to-driver
skew, whereas your brief description refers to "startup".

Regards,
Tony

-----Original Message-----
From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On
Behalf Of Akhilesh CHANDRA
Sent: Monday, May 14, 2007 4:18 AM
To: ibis@server.eda-stds.org
Cc: Akhilesh CHANDRA
Subject: [IBIS] How we can model startup time in IBIS.

 

Hello Experts,

  I am doing IBIS model of an IO operating at 800MHZ frequency. It have
startup time of 3nsec. After 3ns design gives output of 800mhz
frequency. If I model this time in waveform database of IBIS models the
I have over clocking issue and design is not work at this high
frequency. Can you help me to model this startup time. Is anyone make
IBIS model of such designs.

Regards
Akhilesh


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Received on Mon May 21 03:20:15 2007

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