RE: [IBIS] About Some IBIS Specifications

From: Todd Westerhoff <twesterh_at_.....>
Date: Fri Jul 06 2007 - 10:50:50 PDT
Yasser,

 

I maintain one of the key reasons we perform signal integrity analysis is to derive an interconnect
delay (based on simulation) that we can then put back into a system timing model to see if an
interface meets timing requirements.

 

The first set of parameters you've listed don't affect the simulated _waveform_ in any way - but
they do affect the way that waveform is _measured_ to derive an interconnect delay.

 

[Temperature Range] combines with [Voltage Range] and min/typ/max table data to define the operating
conditions (process, voltage, temperature) under which IBIS were derived, and therefore say what
operating conditions a simulation using those models represents..  

 

Todd.


Todd Westerhoff
VP, Software Products
SiSoft
6 Clock Tower Place, Suite 250
Maynard, MA 01754
(978) 461-0449 x24
twesterh@sisoft.com
www.sisoft.com

  _____  

From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Yasser Sabry
Sent: Monday, July 02, 2007 10:41 AM
To: ibis@eda-stds.org
Cc: Yasser Sabry
Subject: [IBIS] About Some IBIS Specifications

 

Dear all,

I want to make sure from some IBIS specifications if you don't mind

I understand that the blow listed subparamters or keywords don't affect the simulation results (or
simulation procedure carried out by the simulation tool). I want to make sure that no action is
assumed to be taken from the simulation tool towards the below listed keywords/subparamters : 

 

*	Vmeas, Vref, Cref. Rref, Cref_rising, Cref_falling, Rref_rising, Rref_falling, Vref_rising,
Vref_falling, Vmeas_rising, Vmeas_falling, ,Rref_diff, Cref_diff under [Model Spec] 
*	[Temperature Range]
*	[Test Data]
*	[Test Load]

Your feedback is highly appreciated

Thanks & BR,
Yasser Sabry

 


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Received on Fri Jul 6 10:51:13 2007

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