RE: [IBIS] Extracting V-T waveform data for the purpose of modeling a CMOS buffer

Hi Nam,

Arpad has explained this in a lecture on IBIS. The lecture slide can be
found at

http://download.intel.com/education/highered/signal/ELCT762/Class17_18_I
BIS_io_buffer_class.ppt
<http://download.intel.com/education/highered/signal/ELCT762/Class17_18_
IBIS_io_buffer_class.ppt> 

 

Slide-24 in this lecture explain, why 4-VT tables?

 

Hope, this presentation will help you.

 

Thank you,

Muniswar

________________________________

From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of
Nguyen, Duynam
Sent: Friday, May 02, 2008 12:48 AM
To: ibis@eda.org
Subject: [IBIS] Extracting V-T waveform data for the purpose of modeling
a CMOS buffer

 

In section 3.2 of the 09/15/05 "IBIS MODELING COOKBOOK For IBIS Version
4.0" document, it is stated,

"... for each simulation corner, four V-T data sets are generally
recommended. Two waveforms - either featuring a load to ground or a
relatively low voltage - are generated for the buffer output switching
low to high. The other two waveforms - both featuring a load to Vcc or a
relatively high voltage - are generated for the buffer output switching
high to low."

Why do we need two waveforms for each buffer output transition ? 

 

Thanks,

Nam    


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