RE: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedance

From: Tom Dagostino <tom_at_.....>
Date: Tue Aug 19 2008 - 00:32:56 PDT
My experience with simulators is consistent with IBIS' recommendations. If
you put reactive loads in the VT curve load many times the simulations blow
up.  If you allow the SI simulator to simulate the actual load seen by the
driver - a transmission line plus package plus any other parasitics, the
simulations tend to match measurements.  As a model maker you will never
know what kinds of loads the end user places on the driver.  So you cannot
anticipate what reactive load to put in the model.  

 

Once you get on the board and assuming (and at times this is a big
assumption) there is power/ground plane beneath the trace from the driver to
the load, the load seen by the driver will be a transmission line load.  If
the end product's board looks like lumped RLCs there are going to be
problems.

 

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065

503-430-1285 FAX
tom@teraspeed.com
www.teraspeed.com

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827 

 

From: Sudarshan H N [mailto:hn.sudarshan@gmail.com] 
Sent: Monday, August 18, 2008 11:27 PM
To: tom@teraspeed.com
Cc: Chetana Raghuwanshi; ibis@server.eda.org; ibis-users@server.eda.org;
owner-ibis-users@server.eda.org
Subject: Re: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver
impedance

 

HI,

I had a similar discussion about the value of the Rfixture some time back
with the IBIS group, and that time the conclusion was, as you said we should
select Rfixture close to the impedance seen by the driver on the board i.e,
around 50ohm. But the exact value might be different and hence these  V-t
curves in IBIS will just give one set of values for given Rfixture,  and
board level simulation tools will use these V-t curves as a reference to get
the actual V-t waveforms for a given load. 

Still my doubt is, the pad will see some value of RLC on the board, and IBIS
discourages to use reactive loads when generating Vt curves. So how much
accuracy these V-t curves will give , assuming its only generated with
Rfixture and not with other reactive loads.

Regards
Sudarshan

On Mon, Aug 18, 2008 at 10:08 PM, Tom Dagostino <tom@teraspeed.com> wrote:

No, no and no.

 

The load resistor used for extracting the VT waveforms should represent the
load seen by the driver on the circuit board.  Most reasonable circuit
boards will have trace impedances between 40 and 75 Ohms and usually the
design targets 50 Ohms.  So the IBIS model should characterize the buffer
into an impedance close to that. The generally accepted value is 50 Ohms.
It has nothing at all to do with the output impedance of the driver.  You
are not trying to match load/output impedance or maximize power transfer,
you are trying to get a macro model to be characterized near its operating
conditions.

 

There are no such things as IV VT curves. There are no loads associated with
extracting IV curves.

 

Extending the simulation time may or may not "fix" IV/VT curve mismatches.
Extending simulations times will only fix mismatches if the original
simulations did not allow the VT waveforms to reach their final value.  If
you have a problem understand the cause before jumping to a solution.  Just
jumping to a solution in most cases will not work.

 

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065

503-430-1285 FAX
tom@teraspeed.com
www.teraspeed.com

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827 

 

From: owner-ibis-users@server.eda.org
[mailto:owner-ibis-users@server.eda.org] On Behalf Of Chetana Raghuwanshi
Sent: Monday, August 18, 2008 6:51 AM
To: Sudarshan H N
Cc: ibis@server.eda.org; ibis-users@server.eda.org;
owner-ibis-users@server.eda.org
Subject: Re: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver
impedence

 

Hi Sudarshan,

You are right. My concern is IV VT mismatch error.
How would it disappear by increasing the simulation time ?

Best Regards
Chetana

--------------------------------------------------------
Chetana Raghuwanshi
CTO / Process & Library Technology
NXP Semiconductors India
NXP Block C, 4th Floor
MFAR Manyata Tech Park
Nagavara, Bangalore-560045
Tel : +91 80 4024 7072
--------------------------------------------------------
Error! Filename not specified."Sudarshan H N" <hn.sudarshan@gmail.com>


"Sudarshan H N" <hn.sudarshan@gmail.com> 
Sent by: 

owner-ibis-users@server.eda.org 

2008-08-18 06:43 PM


Error! Filename not specified.

To

Error! Filename not specified.
"Chetana Raghuwanshi" <chetana.raghuwanshi@nxp.com>


Error! Filename not specified.

cc

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ibis-users@server.eda.org, ibis@server.eda.org


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Subject

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[IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence

 


Error! Filename not specified.

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Hello Chetana,

You can use any of the 2 values for Rfixture to generate Vt curves. There is
no rule that , your Rfixture should match to the PMOS or NMOS driver
resistance. But you should always use one value to generate the one set of
rising and falling waveforms(experts, correct me if i am wrong). If you are
seeing any errors with respect to IV and Vt curve mismatch , just simulate
for more time so that it will reach the saturation.

Regards
Sudarshan

On Mon, Aug 18, 2008 at 6:37 PM, Chetana Raghuwanshi <
<mailto:chetana.raghuwanshi@nxp.com> chetana.raghuwanshi@nxp.com> wrote: 

Hello Experts,

One of my IO cell has a buffer with different PMOS and NMOS impedences.
PMOS impedence is approx 200 Ohms and that for NMOS is 96 Ohms.
In this case what should be the value of Rfixture for calculating IV VT
curves ?
Would it be Rfixture1 for calculating pull down and falling waveforms and
Rfixture2 for calculating pull up and rising waveforms ?
If I do rise/pullup and fall/pulldown simulations with different Rfixture
values, is it acceptable ?

Best Regards
Chetana


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