RE: [IBIS] Re: [IBIS-Users] Simulating IBIS at the maximum frequency

Yes, the V/T table curves are shifted back toward t=zero, and it is
important that all waveforms of the same direction (for example all
[Rising Waveform]s) must be shifted by the same time offset.

But people have different conventions with regard to synchronizing the
shifting of the typ/min/max corners. Some people determine the smallest
lead time, which is usually on the max corner, and take that much out of
all three corners. This is easy because you only have to delete some
table rows and subtract some offset from all time values, easily
accomplished with just a spreadsheet. Some will remove lead time from
each corner independently. I would write code to do this before trying
it with a spreadsheet, since it sometimes involves resampling the
waveform points.

Lance Wang presented on one aspect of the overclocking topic at an IBIS
summit:

http://www.vhdl.org/pub/ibis/summits/feb07/wang.pdf

My own observation is that simulators at one time had trouble with IBIS
waveforms longer than 1/2 a clock period, but no longer do.

Mike

-----Original Message-----
From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On
Behalf Of Scott McMorrow
Sent: Monday, May 18, 2009 11:17 AM
To: g-m@ti.com
Cc: ibis-users@server.eda.org; ibis@server.eda.org
Subject: [IBIS] Re: [IBIS-Users] Simulating IBIS at the maximum
frequency

Gowtham

Since time is relative in IBIS model simulations, what you do is to
normalize the V/T table timing, by shifting the slower corner curves
back towards zero.  Essentially, you remove any leading static values
from the curves, prior to the edge transitions.

Scott


Gowtham M wrote:
> Hello,
>
> How do we ensure that IBIS model can be correctly simulated at the 
> highest possible frequency? Suppose, I have a buffer which is expected

> to work at 100MHz. Hence, the VT table should be at most 1 / ( 2 * 
> 100M ) = 5ns wide.
>
> If the buffer is designed such that it can just meet this requirement 
> in min (slow) corner. The problem that I am facing is that I cannot 
> represent all of typ/min/max transitions within this window of 5ns 
> because of variations in buffer delay across corners.
>
> How do I create an IBIS model that can be correctly simulated at 
> 100MHz in such cases?
>
> Thanks for your help.
>
> Gowtham
>

--
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

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