[IBIS] Asian IBIS Summit (Yokohama) - Agenda

From: Bob Ross <bob@teraspeed.com>
Date: Tue Nov 06 2012 - 17:21:41 PST
All:

 

The Agenda showing nine presentations is below. Registration

information is given at the end. We are looking forward to

seeing everyone in Yokohama.

 

Bob Ross

Teraspeed Consulting Group

 

Atsushi Ishikawa

JEITA EC Center

 

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      A S I A N   I B I S   S U M M I T    I N F O R M A T I O N

 

Time/Date:  Friday November 16, 2012, 13:00 to 18:00

            Meeting starts at 13:30

 

Location:   Pacifico Yokohama Annex Hall

            1-1-1, Minato Mirai, Nishi-ku

            Yokohama, JAPAN

 

            http://www.pacifico.co.jp/english/index.html

 

Organizational Sponsors:

            Japan Electronics and Information Technology Industries

               Association (JEITA)

            IBIS Open Forum

 

Sponsors:   ANSYS

            ATE Service Corporation

            Cadence Design Systems

            Mentor Graphics Corporation

            Zuken

 

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         I B I S  S U M M I T  M E E T I N G  A G E N D A

 

13:00   SIGN IN

 

13:30   Meeting Welcome

          Haruhiro Saito (Sony, JEITA EC Center, Japan)

          Lance Wang (IO Methodology, Vice Chair IBIS Open Forum)

 

13:40   IBIS 5.1 An Overview 

          Michael Mirmak (Intel Corporation, USA)

 

14:05   IBIS Parser Update

          Bob Ross (Teraspeed Consulting Group, USA)

 

14;30   S-Parameter: What You Can Read, What You Have To Read

          Shinichi Maeda (KEI Systems, Japan)

 

15:00   Chip PDN Model for Power Aware Signal Integrity Analysis

          Jack W.C. Lin# and Raymond Y. Chen##

          (Cadence Design Systems, #ROC, ###USA)

 

15:30   BREAK

 

15:45   The Voice from Practical Designing with SI Simulation

          Hironari Kibe (Zuken, Japan)

 

16:10   IBIS Validation Method Review

          Lance Wang (IO Methodology, USA)

 

16:35   Over-clocking Model Validation

          Yasuki Torigoshi (Toshiba Corporation, Japan)

 

17:00   Designing DDR3 System Using Static Timing Analysis in

        Conjunction with IBIS Simulations

          Taranjit Kukal#, Zhangmin Zhong##, and Heiko Dudek###

          (Cadence Design Systems, #India, ##China, ###Germany)

 

17:30   The Application of Simulation Kit Using USB3.0 IBIS-AMI

        Model

          Motoaki Matsumura (Fujitsu Semiconductor, Japan)

 

17:55   Concluding Items

 

18:00   END OF MEETING

 

----------------------------------------------------------------

Registration:

 

  Please Register with the information below:

 

    Name:

    E-mail address:

 

    Company:

    Country:

 

  Send to BOTH:

 

     Bob ROSS, Teraspeed Consulting Group    bob@teraspeed.com

     Atsushi ISHIKAWA, JEITA EC Center       a-ishikawa@jeita.or.jp

 

 

--

Bob Ross

Teraspeed Consulting Group, LCC

http://www.teraspeed.com

bob@teraspeeed.com

Direct : 503-246-8048

Teraspeed Labs: 503-430-1065

Headquarters: 401-284-1827

 

Teraspeed is a registered service mark of Teraspeed Consulting Group LLC

 


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Received on Tue Nov 6 17:22:24 2012

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