[IBIS] European IBIS Summit Agenda - May 15, 2013

From: Bob Ross <bob@teraspeed.com>
Date: Mon May 06 2013 - 10:48:57 PDT
All:

 

The 16th European IBIS Summit is on Wednesday afternoon and

follows the IEEE Workshop on Signal and Power Integrity:

 

  http://www.spi2013.org/

 

Below is the meeting agenda.  The IBIS meeting is free.  If

you plan to attend, please register with Lance Wang as noted at

the end.

 

Lance Wang

IO Methodology

 

------------------------------------------------------------------

 

                AGENDA, EUROPEAN IBIS SUMMIT MEETING

                      Wednesday, May 15, 2013

 

                     Hyatt Regency Paris Etoile

             (NOTE: formerly Hotel Concorde La Fayette)

                     3, Place du Général Koenig 

                         Paris, France, 75017

 

                     http://tinyurl.com/bna6xrz

                                          

               Room: Pissaro-Cezanne (Check at Entrance)

 

------------------------------------------------------------------

 

13:00  SIGN IN

 

13:15  WELCOME AND INTRODUCTIONS

       Lance WANG, IO Methodology, IBIS Vice Chair, USA

 

13:30  IBIS Modeling for Load Dependent Current Model Differential

       Driver

       Lance WANG, IO Methodology, USA

 

13:50  X2IBIS: Using X-parameters to Generate IBIS Models

       Thomas COMBERIATE and Jose SCHUTT-AINE

       University of Illinois, USA

       (Presented by Thomas COMBERIATE, USA)

 

14:30  Thevenin's Theorem Revisited. A New Approach to IC Buffer

       Modeling and It's Relation to IBIS

       Igor STIEVANO*, Cherif DIOUF**, Mihai TELESCU**, N. TANGUY**,

       and Flavio CANAVERO*

       *Politecnico di Torino, Italy;      

       **Université Européenne de Bretagne, Université de Brest,

       France

       (Presented by Mihai TELESCU, France)      

 

15:00  A Novel Two-Port Behavioral Model for I/O Buffer

       Overclocking Simulation

       Wael DGHAIS,

       University of Averio, Institue of Telecommunications,

       Portugal

 

15:30  BREAK (15 Minutes)

 

15:45  Novel Extraction of Table-Based I-Q Behavioral Model for

       High-Speed Digital Buffers/Drivers

       Wael DGHAIS,

       University of Averio, Institue of Telecommunications,

       Portugal

 

16:15  Interconnect Modeling Update - EMD Specification

       Randy WOLFF, Micron Technology, USA

 

16:45  Ibischk5 Specification and Parser

       Bob ROSS* and Mike LABONTE**,

       *Teraspeed Consulting Group and

       **Signal Integrity Software (SiSoft), USA

       (Presented by Anders EKHOLM, Ericsson, Sweden)

 

17:30  DISCUSSION AND CLOSING REMARKS

       Lance WANG, IO Methodology, USA

 

18:00  END OF MEETING

 

------------------------------------------------------------------

 

REGISTRATION INFORMATION

 

People involved in IBIS Model development, EDA tool development, and

digital circuit design are invited to participate to the Summit

meeting. If you plan to participate, please register with the

information below:

 

   Name:

   E-mail address:

   Company:

   Telephone:

 

Send to:

 

   Lance WANG (lwang@iometh.com)

 

SPONSORS:

 

   Micron Technology and Zuken

SPI CONFERENCE INFORMATION AND TRAVEL DIRECTIONS

 

   See http://www.spi2013.org/ for travel directions,

   IBIS meeting hotel and other information.

 

------------------------------------------------------------------

 

--

Bob Ross

Teraspeed Consulting Group, LCC

http://www.teraspeed.com

bob@teraspeeed.com

Direct : 503-246-8048

Teraspeed Labs: 971-279-5325

Headquarters: 401-284-1827

 

Teraspeed is a registered service mark of Teraspeed Consulting Group LLC

 

 


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Received on Mon May 6 10:49:48 2013

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