****************************************************************************** ****************************************************************************** BIRD ID#: 95.2 ISSUE TITLE: Power Integrity Analysis using IBIS REQUESTER: Syed Huq, Vinu Arumugham, Zhiping Yang - Cisco Systems, Inc.; Bob Ross, Teraspeed Consulting Group DATE SUBMITTED: December 13th, 2004 DATE REVISED: January 28th, 2005, March 8, 2005 DATE ACCEPTED BY IBIS OPEN FORUM: PENDING ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: Power Integrity Analysis which includes Current switching profile of the Core as well as Simultaneous Switching Noise (SSN) of the Input/Output (I/O) stages of a buffer needs to be analyzed through IBIS. This BIRD proposes a modeling scheme to solve this. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: Power Integrity Analysis from a modeling perspective has been split into multiple tasks. Current into the power and ground rails are needed to give a more accurate analysis for ground and power bounce associated with simultaneous switching noise. Solving the Simultaneous Switching Noise (SSN) will be achieved through the use of IvsT tables and Z_VDDQ parameters as part of this proposal. The following keyword is positioned under the [Rising Waveform]/[Falling Waveform] keyword: |============================================================================== | Keywords: [Composite Current] | Required: No | Description: Describes the shape of the rising and falling edge | current waveforms from the power supply measured through | the power pin terminal illustrated more fully in the Usage | Rules. | Sub-params: R_zvddq, R L_zvddq, C_zvddq_typ, G_zvddq | Usage Rules: The [Composite Current] keyword is positioned under the | [Rising Waveform] (for rising waveform currents) and | [Falling Waveform] (for falling waveform currents. The keywords | are followed by optional on-die parasitic die subparameters and | then a table of current versus time rows (I-T) that | describe the shape of a current waveform. These I-T tables | inherit the fixture test load of the [Rising Waveform] | or [Falling Waveform] R/L/C/V_fixture and R/L/C_dut | subparameters. | | The [Composite Current] keyword is optional. It can be omitted, | or it can be positioned under a few, but not all of the rising | and falling waveform tables. | | The listed subparemeters, R_zvddq, L_zvddq, C_zvddq, and G_zvddq, | describe the impedance path between the power pin terminal and | ground (see Other Notes below). The first three subparameters | describe a series path of resistance, inductance and capacitance. | The forth subparameter describe a separate path in parallel to | the series path and also between the power pin terminal and | ground. | | These subparameters are optional, but if any are missing, they | take on a default value of zero. Thus C_zvddq, if missing, opens | the series path, and if R_zvddq is missing, the resistance is | assumed zero. If G_zvddq is missing, it is not included in the | model | | The I-T table follows these subparameters. The table itself | consists of one column of time points, then | three columns of current points in the standard typ, min, and | max format. The four entries must be placed on a single line and | must be separated by at least one white space. All four | columns are required. However, data is only required in the | typical column. If minimum or maximum data is not available, | use the reserved word "NA". The first value in the time column | need not be '0'. Time values must increase as one parses down | the table. The waveform table can contain a maximum of 1000 | data points. | | The following diagramss illustrate a typical configurating which | a [Rising Waveform] or [Falling Waveform is extracted. The | DUT die is modified to include the Power Pin and Ground Pin. | | | Power Pin | | | | | | | PACKAGE | TEST FIXTURE | ____|____ | | | DUT | L_dut R_dut | L_fixture R_fixture | | die |---@@@@@--/\/\/\--o-----|--@@@@---o---/\/\/\--- V_fixture | |_________| | | | | | | | | | | | | | | | C_dut === | === C_fixture | | | | | | |_______________________|_____|_________|___ | Ground Pin | GND | | | The [Composite Current] direction is shown with respect to the | Power Pin and the new subparameters are added to the DUT die. | These subparameters do not effect the [Rising Waveform and | [Falling Waveform] table extractions, but give added equivalant | circuit detail for more accurate power pin current calculations. | | ! [Composite Current] | <------ | __________________________________ Rower Pin | | | ___________________|_______________________ | | | | | | ___________|______________ | | | ____|____ | | | | | | | | | DUT | | | | R_zvddq | | | die | | | |_________| | | | | | ____|____ ____|____ ____|____ | | | | | | | | I/O | | | | | L_zvddq | | G_zvddq | | die |-------------- To L_dut | | |_________| |_________| |_________| | | | ____|____ | | | | | | | | | | | | | C_zvddq | | | | | | |_________| | | | | | |___________|______________| | | | | | | |___________________|_______________________| | | | |________________________________ Ground Pin | | | | Other Notes: The internal networks for the DUT die 'Black Box' are shown | below to illustrate the effects that the equivalent circuit | are intended to describe. The Power Pin terminal is ahown as | VDDQ, and the Ground Pin terminal is shown as GND. | | | VDDQ | Black Box (**) o | ___________________________________________________________________________||__ || || | || || | || v| | || -------- -------- | | || | | | | | | || ____________________________________________|L_VDDQ|_|R_VDDQ|__| | || | | | | | | | | | | || | | | | | -------- -------- | || ----- | | | | | || | E | | / | | | || | S | ---------------- \ P_| --- PowerClamp | || | R | | Pre-Driver | / || / \ | || ----- | Circuit | \ ||_ --- | || | | powered by | | | | | || | | VDDQ | | | | | I_sig | || ----- ---------------- | | | | -------> | || | E | | o-----o--|----o---------------------------o || | S | | | | | | | Sig || | | L | | | | / | | | | || I_byp| ----- I_pre| |I_term| \ N_| v --- GNDClamp | || | | | | | / || I_cb / \ | || v | v | v \ ||_ --- | || ----- | | | | ------ ------- | || ----- C_p+b | | | | | | | | || |___________________|_________|_____|_______|___|L_GND|_|R_GND|__ | || | | | | | | || ------ ------- | | || | | || | | ||____________________________________________________________________________|__| | | | o | GND | | (**) I-T - current through VDDQ terminal. | | Other elements typically in a more detailed model are | | I_byp - Bypass current | I_pre - Pre-Driver current | I_cb - Crow-bar current | I_term - Termination current (optional) | L_VDDQ - On-die inductance of I/O Power | R_VDDQ - On-die resistance of I/O Power | L_GND - On-die inductance of Ground | R_GND - On-die resistance of Ground | C_p+b - Bypass + Parasitic Capacitance | ESR - Equivalent Series Resistance for on-die Decap | ESL - Equivalent Series Inductance for on-die Decap | | | The subparameters R_zvddq, L_zvddq, C_zvddq and G_zvddq represent | and effective impedance of the internal Power pin to Ground pin | elements, as extracted from the terminals. In the future, the ICM | format might proivde more accurate detail, if needed. | NOTE: The Power Pin terminal in most cases is the [Pullup Reference], | or the default [Voltage Range] value. This [Pullup Reference] can | also be GND, as in some *_ECL technologies, and the Ground Pin is the | more negative reference. In such cases, the [GND Clamp Reference] | value should be defined. | | If [POWER Clamp Reference] or [GND Clamp Reference] are different | than the [Pullup Reference] or [Pulldown Reference] voltages, | the model may not account for all of the currents. However, the | simulatiion should still closely approximate the current transients. | | The [Composite Current] can still be defined for Model_types with } out the [Pullup] keywords (such as Open_drain) because the [Pullup | Reference] or [Voltage Range] are still required. Pre-driver and | other internal paths still exist. | | NOTE: In most cases six [Composite Current] tables are recommended | for accurate modeling. The first four tables correspond to the | recommended fixture conditions for [Rising Waveform] and [Falling | Waveform] tables (normally 50 ohm loads to Vdd and GND). Two | additional waveforms for no load conditions (such as with an R_fixure | of 1.0 megaohm are useful. However, some EDA tools may use only | the first four waveforms. So these additional open load waveform | I-T tables should be in [Rising Waveform] and [Falling Waveform] | tables positioned after the other V-T tables to maintain the best | output response accuracy. These extra two tables do not apply | for any of the Open-drain and Open-source technologies or for | ECL technologies. | | When the [Model] is configured differentially with the [Diff Pin] | keyword, the individual I-T currents for each [Model] is used as | an approximation. This summation may not be as accurate as the | the actual measured currents under actual operation. | | The [Composite Current] table can be derived from currents measured | at the GND node that have been transformed by combining with the | current at the output pin. | | The [Pin Mapping] keyword is used to docuemnt the voltage rails | of several buffers are combined. This combination includes the | effective impedances describe for each buffer | | The [Composite Current] keyword is not designed to accurately | document the effects of controlled switching buffers such as | those defined with [Submodel] or [Driver Schedule] keywords. |------------------------------------------------------------------------------ | [Rising Waveform] R_fixture = 50.0 V_fixture = 0.0 | ... | ... | Rising Waveform table | ... [Composite Current] R_zvddq = 2.0m L_zvddq = 0.2n C_zvddq = 2.0p G_zvddq = 2.0u | | Time I(typ) I(min) I(max) 0 4.243E-05 NA NA 4.00E-11 4.244E-05 NA NA 8.00E-11 4.242E-05 NA NA 1.20E-10 4.265E-05 NA NA 1.60E-10 3.610E-05 NA NA 2.00E-10 3.903E-03 NA NA .. .. .. 3.80E-09 2.012E-02 NA NA 3.84E-09 2.012E-02 NA NA 3.88E-09 2.012E-02 NA NA 3.92E-09 2.012E-02 NA NA 3.96E-09 2.012E-02 NA NA 4.00E-09 2.012E-02 NA NA | [Falling Waveform] R_fixture = 50.0 V_fixture = 1.8 | ... | ... | Falling Waveform table | ... [Composite Current] R_zvddq = 2.0m L_zvddq= 0.2n C_zvddq = 2.0p G_zvddq = 2.0u | | Time I(typ) I(min) I(max) 0 4.302E-05 NA NA 4.00E-11 4.299E-05 NA NA 8.00E-11 4.304E-05 NA NA 1.20E-10 4.287E-05 NA NA 1.60E-10 4.782E-05 NA NA 2.00E-10 1.459E-04 NA NA .. .. .. 3.80E-09 4.933E-05 NA NA 3.84E-09 5.211E-05 NA NA 3.88E-09 5.490E-05 NA NA 3.92E-09 5.441E-05 NA NA 3.96E-09 4.842E-05 NA NA 4.00E-09 4.244E-05 NA NA | | ... etc. | |------------------------------------------------------------------------------ ****************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: Power Integrity Analysis has become a significat part of Signal Integrity Simulations and Analysis. Core voltages are going down with process enhacementand, I/O speeds are increasing, it is critical that high-speed applications solve Power Integrity issues on the die, package and PCBs combined. System failures can be traced to poor Power Integrity Designs. During the DesignCon2004 Power Integrity Panel, these issues were discussed. It was suggested to explore a solution through the IBIS commitee and hence this BIRD proposal. Several discussions were conducted(3/12,5/14,6/8,7/16,8/24)with the IBIS Futures Meetings. ****************************************************************************** ADDITIONAL INFORMATION SECTION: Other Power Integrity Related BIRDs: Linkage to a Core model will be achieved by BIRDXX (TBD). Linkage to an ICM model will be achieved by BIRDYY (TBD). Linkage to a Gate Modulation model will be achieved by BIRD97. ****************************************************************************** ANY OTHER BACKGROUND INFORMATION: This proposal is based on various past work done by many IBIS contributors and they are listed in no particular order. Links to ICEM are also listed: DesignCon2004 PDN Simulation panel proceedings material and slides: http://home.att.net/~istvan.novak/papers.html BIRD42.3: Modeling Current Waveforms C.Kumar, Bob Ross IBIS and ICEM interaction: B.Ross, Microelectronic Journal Nov16,2003 ICEM: ---- EMC for Component, Integrated circuits Electrical Model(ICEM) 93/XX/CDC, Project number 62014-3 Cookbook for Integrated Circuit model ICEM, Project number 62014-3 IBIS Summits: ------------- EMC model for prediction of parasitic emission, E.Sicard, Mar2001 Electromagnetic Compatibility simulation of Printed Circuit Board, M.Christian, Mar2001 ICEM - Proposal IEC62014-3, J.C.Perrin, Mar2001 Advances of the ICEM model for Emission of Integrated Circuit, S.Calvet, Jan2001 Adding On-Chip Capacitance in IBIS Format for SSO Simulation, R.Chen, Jan2004 Simultaneous Switching Noise(SSN)Modeling, B.Unger Jan2000 Crossbar-current out of CMOS-IBIS-Models, K.Koller & G.Bannert, Mar2002 IC-Emit Comparing Simulated/Measured IC Emission Spectrum, E.Sicard & A.Soubeyran Feb2004 ********************************************************************************* REVISION HISTORY CHANGES: Replace following BIRD95.1 lines: |*Power Integrity Analysis from a modeling perspective has been split into |*two tasks. |*1)Solving the Simultaneous Switching Noise (SSN) on the I/O level using current |* and future IBIS syntax. This will be achieved through IvsT tables. |*2)Solving the Core Current Switching profile using the ICEM (Integrated circuits |* Electrical Model specification, Project number 62014-3). This will be achieved |* by a call statement within IBIS calling an ICEM model. Using v4.1 IBIS syntax. replace: Current into the power and ground rails are needed to give a more accurate analysis for ground and power bounce associated with simultaneous switching noise. replace: | Keywords: [Series Composite Current] with: replace: | Description: Describes the shape of the rising and falling edge | current waveforms from the power supply measured through | R_VDD(see diagram). This includes Pre-driver, Crow-bar current, | on-die I_bypass and I_term(see diagram). replace: | Usage Rules: The [Series Composite Current] keyword is positioned under the replace: | | | -------- -------- (**) | | | | |<--- | _____________________________________________|L_VDDQ|_|R_VDDQ|__VDDQ | | | | | | | | | | | | | | | | -------- -------- | ----- | | | | | | E | | / | | | | S | ---------------- \ P_| --- PowerClamp | | R | | Pre-Driver | / || / \ | ----- | Circuit | \ ||__ --- | | | powered by | | | | | | | VDDQ | | | | | I_sig | ----- ---------------- | | | | -------> | | E | | o-----o--|----o---------- | | S | | | | | | | | | L | | | | / | | | |I_bypass| ----- I_pre| |I_term| \ N_| v --- GNDClamp | | | | | | / || I_cb / \ | v | v | v \ ||_ --- | ----- | | | | ------ ------- | ----- C_p+b | | | | | | | | | |___________________|_________|_____|_______|___|L_GND|_|R_GND|__GND | | | | | | ------ ------- | | I_bypass - Bypass current | I_pre - Pre-Driver current | I_cb - Crow-bar current | I_term - Termination current (optional) | L_VDDQ - On-die inductance of I/O Power | R_VDDQ - On-die resistance of I/O Power | L_GND - On-die inductance of Ground | R_GND - On-die resistance of Ground | C_p+b - Bypass + Parasitic Capacitance | ESR - Equivalent Series Resistance for on-die Decap | ESL - Equivalent Series Inductance for on-die Decap | | (**) - Current measure point ***************************************************************************