****************************************************************************** ****************************************************************************** BIRD ID#: 116 ISSUE TITLE: Add IBIS-ISS to [External Model] and [External Circuit] as a Supported Language REQUESTER: Arpad Muranyi, Mentor Graphics DATE SUBMITTED: September 29, 2010 DATE REVISED: DATE ACCEPTED BY IBIS OPEN FORUM: ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: The IBIS-ISS specification defines useful and much-needed features through a standardized SPICE language. [External Model] and [External Circuit] already makes use of Berkeley SPICE as a language. Adding IBIS-ISS as another language supported by these keywords would extend the current capabilities of IBIS significantly through the usage of IBIS-ISS subcircuits, with minimal changes in the specification and little implementation effort in EDA tools. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: The Language subparameter of the [External Model] and [External Circuit] keywords shall have one additional option, namely "IBIS-ISS". The usage rules of the IBIS-ISS language shall be the same as the rules for the existing Berkeley SPICE language option, with the exception that parameter passing shall be allowed and supported for those parameters which are defined on the IBIS-ISS subcircuit definition line. Replace all occurences of: SPICE, Verilog-A(MS), VHDL-A(MS) SPICE, Verilog-A(MS) or VHDL-A(MS) SPICE, Verilog-A(MS) and VHDL-A(MS) with: SPICE, ISS, Verilog-A(MS), VHDL-A(MS) SPICE, ISS, Verilog-A(MS) or VHDL-A(MS) SPICE, ISS, Verilog-A(MS) and VHDL-A(MS) Replace all occurences of: SPICE, VHDL-A(MS), Verilog-A(MS) SPICE, VHDL-A(MS) or Verilog-A(MS) SPICE, VHDL-A(MS) and Verilog-A(MS) with: SPICE, ISS, VHDL-A(MS), Verilog-A(MS) SPICE, ISS, VHDL-A(MS) or Verilog-A(MS) SPICE, ISS, VHDL-A(MS) and Verilog-A(MS) On pg. 99 add the following lines between the paragraphs which begin with "SPICE" and "VHDL-AMS": | "ISS" refers to the "IBIS Interconnect SPICE Subcircuits Specification | (IBIS-ISS)", developed by the members of the IBIS Open Forum. On pg. 106 replace the following lines: | Language: | | Accepts "SPICE", "VHDL-AMS", "Verilog-AMS", "VHDL-A(MS)" | or "Verilog-A(MS)" as arguments. The Language subparameter | is required and must appear only once. with these lines: | Language: | |* Accepts "SPICE", "ISS", "VHDL-AMS", "Verilog-AMS", "VHDL-A(MS)" | or "Verilog-A(MS)" as arguments. The Language subparameter | is required and must appear only once. On pg. 107 replace the following lines: | The circuit_name entry provides the name of the circuit to be | simulated within the referenced file. For SPICE files, this | is normally a ".subckt" name. For VHDL-AMS files, this is with these lines: | The circuit_name entry provides the name of the circuit to be |* simulated within the referenced file. For SPICE and ISS files, this | is normally a ".subckt" name. For VHDL-AMS files, this is On pg. 107 replace the following lines: | Parameter passing is not supported in SPICE. VHDL-AMS and | VHDL-A(MS) parameters are supported using "generic" names, and | Verilog-AMS and Verilog-A(MS) parameters are supported using | "parameter" names. with these lines: | Parameter passing is not supported in SPICE. VHDL-AMS and | VHDL-A(MS) parameters are supported using "generic" names, and | Verilog-AMS and Verilog-A(MS) parameters are supported using |* "parameter" names. ISS parameters are supported for all ISS |* parameters which are defined on the subcircuit definition |* line. On pg. 119 add these lines after the SPICE example: |------------------------------------ | Example [External Model] using ISS: |------------------------------------ | [Model] ExBufferISS Model_type I/O Vinh = 2.0 Vinl = 0.8 | | Other model subparameters are optional | | typ min max [Voltage Range] 3.3 3.0 3.6 | [Ramp] dV/dt_r 1.57/0.36n 1.44/0.57n 1.73/0.28n dV/dt_f 1.57/0.35n 1.46/0.44n 1.68/0.28n | [External Model] Language ISS | | Corner corner_name file_name circuit_name (.subckt name) Corner Typ buffer_typ.spi buffer_io_typ Corner Min buffer_min.spi buffer_io_min Corner Max buffer_max.spi buffer_io_max | | List of parameters Parameters sp_file_name Parameters C1_value R1_value | | Ports List of port names (in same order as in ISS) Ports A_signal my_drive my_enable my_receive my_ref Ports A_puref A_pdref A_pcref A_gcref A_extref | | D_to_A d_port port1 port2 vlow vhigh trise tfall corner_name D_to_A D_drive my_drive my_ref 0.0 3.3 0.5n 0.3n Typ D_to_A D_enable my_enable A_gcref 0.0 3.3 0.5n 0.3n Typ | | A_to_D d_port port1 port2 vlow vhigh corner_name A_to_D D_receive my_receive my_ref 0.8 2.0 Typ | | Note: A_signal might also be used instead of a user-defined interface port | for measurements taken at the die pads | [End External Model] | On pg. 123 add these lines after the true differential example in SPICE: |----------------------------------------------------------- | Example of True Differential [External Model] using SPICE: |----------------------------------------------------------- | [Model] Ext_ISS_Diff_Buff Model_type I/O_diff Rref_diff = 100 | | Other model subparameters are optional | | typ min max [Voltage Range] 3.3 3.0 3.6 | [Ramp] dV/dt_r 1.57/0.36n 1.44/0.57n 1.73/0.28n dV/dt_f 1.57/0.35n 1.46/0.44n 1.68/0.28n | [External Model] Language ISS | | Corner corner_name file_name circuit_name (.subckt name) Corner Typ diffio.spi diff_io_typ Corner Min diffio.spi diff_io_min Corner Max diffio.spi diff_io_max | | List of parameters Parameters sp_file_name Parameters c_diff r_diff | | Ports List of port names (in same order as in ISS) Ports A_signal_pos A_signal_neg my_receive my_drive my_enable Ports A_puref A_pdref A_pcref A_gcref A_extref my_ref A_gnd | | D_to_A d_port port1 port2 vlow vhigh trise tfall corner_name D_to_A D_drive my_drive my_ref 0.0 3.3 0.5n 0.3n Typ D_to_A D_drive my_drive my_ref 0.0 3.0 0.6n 0.3n Min D_to_A D_drive my_drive my_ref 0.0 3.6 0.4n 0.3n Max D_to_A D_enable my_enable my_ref 0.0 3.3 0.5n 0.3n Typ D_to_A D_enable my_enable my_ref 0.0 3.0 0.6n 0.3n Min D_to_A D_enable my_enable my_ref 0.0 3.6 0.4n 0.3n Max | | A_to_D d_port port1 port2 vlow vhigh corner_name A_to_D D_receive A_signal_pos A_signal_neg -200m 200m Typ A_to_D D_receive A_signal_pos A_signal_neg -200m 200m Min A_to_D D_receive A_signal_pos A_signal_neg -200m 200m Max | [End External Model] On pg. 125 replace the following lines: | Language: | | Accepts "SPICE", "VHDL-AMS", "Verilog-AMS", "VHDL-A(MS)" or | "Verilog-A(MS)" as arguments. The Language subparameter is | required and must appear only once. | with these lines: | Language: | |* Accepts "SPICE", "ISS", "VHDL-AMS", "Verilog-AMS", "VHDL-A(MS)" | or "Verilog-A(MS)" as arguments. The Language subparameter | is required and must appear only once. On pg. 125 replace the following lines: | The circuit_name entry provides the name of the circuit to be | simulated within the referenced file. For SPICE files, this | is normally a ".subckt" name. For VHDL-AMS files, this is | normally an "entity(architecture)" name pair. For Verilog-AMS | files, this is normally a "module" name. with these lines: | The circuit_name entry provides the name of the circuit to be |* simulated within the referenced file. For SPICE and ISS files, this | is normally a ".subckt" name. For VHDL-AMS files, this is | normally an "entity(architecture)" name pair. For Verilog-AMS | files, this is normally a "module" name. On pg. 126 replace the following lines: | Parameter passing is not supported in SPICE. VHDL-AMS and | VHDL-A(MS) parameters are supported using "generic" names, and | Verilog-AMS and Verilog-A(MS) parameters are supported using | "parameter" names. with these lines: | Parameter passing is not supported in SPICE. VHDL-AMS and | VHDL-A(MS) parameters are supported using "generic" names, and | Verilog-AMS and Verilog-A(MS) parameters are supported using |* "parameter" names. ISS parameters are supported for all ISS |* parameters which are defined on the subcircuit definition |* line. On pg. 129 add these lines after the SPICE example: |-------------------------------------- | Example [External Circuit] using ISS: |-------------------------------------- | [External Circuit] BUFF-ISS Language ISS | | Corner corner_name file_name circuit_name (.subckt name) Corner Typ buffer_typ.spi bufferb_io_typ Corner Min buffer_min.spi bufferb_io_min Corner Max buffer_max.spi bufferb_io_max | | List of parameters Parameters sp_file_name Parameters C1_value R1_value | | Ports List of port names (in same order as in ISS) Ports A_signal int_in int_en int_out A_control Ports A_puref A_pdref A_pcref A_gcref | | D_to_A d_port port1 port2 vlow vhigh trise tfall corner_name D_to_A D_drive int_in my_gcref 0.0 3.3 0.5n 0.3n Typ D_to_A D_drive int_in my_gcref 0.0 3.0 0.6n 0.3n Min D_to_A D_drive int_in my_gcref 0.0 3.6 0.4n 0.3n Max D_to_A D_enable int_en my_gnd 0.0 3.3 0.5n 0.3n Typ D_to_A D_enable int_en my_gnd 0.0 3.0 0.6n 0.3n Min D_to_A D_enable int_en my_gnd 0.0 3.6 0.4n 0.3n Max | | A_to_D d_port port1 port2 vlow vhigh corner_name A_to_D D_receive int_out my_gcref 0.8 2.0 Typ A_to_D D_receive int_out my_gcref 0.8 2.0 Min A_to_D D_receive int_out my_gcref 0.8 2.0 Max | | Note, the A_signal port might also be used and int_out not defined in | a modified .subckt. | [End External Circuit] On pg. 131 add the following lines under the SPICE example: |-------------------------------------- | Example [External Circuit] using ISS: |-------------------------------------- | [External Circuit] BUS_SPI Language ISS | | Corner corner_name file_name circuit_name (.subckt name) Corner Typ bus_typ.spi Bus_typ Corner Min bus_min.spi Bus_min Corner Max bus_max.spi Bus_max | | List of parameters Parameters sp_file_name Parameters C1_value R1_value | | Ports are in same order as defined in ISS Ports vcc gnd io1 io2 Ports int_ioa vcca1 vcca2 vssa1 vssa2 Ports int_iob vccb1 vccb2 vssb1 vssb2 | | No A_to_D or D_to_A required, as no digital ports are used | [End External Circuit] ****************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION IBIS-ISS is a subset of HSPICE (used with the permission of Synopsys) which standardizes the passive elements of HSPICE, primarily for use in interconnect modeling. However, these elements can also be used for buffer modeling, or on-die interconnect modeling, for example. For that reason adding IBIS-ISS as a language supported by the [External Model] and [External Circuit] keywords is a logical extension of the currently available Berkeley SPICE option of IBIS. ***************************************************************************** ANY OTHER BACKGROUND INFORMATION: ******************************************************************************