****************************************************************************** ****************************************************************************** BIRD ID#: 100.2 ISSUE TITLE: Allow Pure Analog *-AMS Models REQUESTER: Ian Dodd, Mentor Graphics; Arpad Muranyi, Intel Corporation DATE SUBMITTED: November 10, 2005 DATE REVISED: January 9, 2006 DATE ACCEPTED BY IBIS OPEN FORUM: PENDING ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: The IBIS 4.1 specification currently requires that some signal ports in *-AMS models must be digital when used together with [External Model]s or [External Circuit]s, and a special syntax using A/D and D/A converters is required when using (analog) SPICE models. There are situations when using the analog-only portions of the *-AMS language(s) may be desirable. For this reason it would be useful to have a mechanism through which *-AMS models containing only analog ports could also be referenced by the [External Model] or [External Circuit] keywords. This BIRD describes a change to the IBIS specification through which this is made possible. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: The Language subparameter of the [External Model] and [External Circuit] keywords shall have two additional options, namely "VHDL-A(MS)" and "Verilog-A(MS)", in which the parentheses indicate that the model uses only the analog subset of the associated *-AMS language. When such references to the *-AMS languages are made in the [External Model] or [External Circuit] keywords, all of the connection ports will be analog, and therefore the requirements of using the A_to_D and D_to_A converters with SPICE models shall also apply to *-A(MS) models. In order to implement this capability, Section 6b in the IBIS specification shall be changed as described below. **In the "LANGUAGES SUPPORTED" section, add before the paragraph starting with **'In addition the "IEEE Standard Multivalue Logic System..."' the following **two paragraphs: ** **"VHDL-A(MS)" refers to the analog subset of VHDL-AMS described above. ** **"Verilog-A(MS)" refers to the analog subset of Verilog-AMS described above. In the specification text as updated by BIRD91.3, replace: | SPICE versus VHDL-AMS and VERILOG-AMS | | SPICE cannot process digital signals. All SPICE input and output signals | must be in analog format. Consequently, IBIS multi-lingual models using | SPICE require analog-to-digital (A_to_D) and/or digital-to-analog (D_to_A) | converters to be provided by the EDA tool. The converter subparameters are | declared by the user, as part of the [External Model] or [External Circuit] | syntax, with user-defined names for the ports which connect the converters | to the analog ports of the SPICE model. The details behind these | declarations are explained in the keyword definitions below. | | To summarize, Verilog-AMS and VHDL-AMS contain all the capability needed to | ensure that a model unit consists of only digital ports and/or analog ports. | SPICE, however, needs extra data conversion, provided by the EDA tool, to | ensure that any digital signals can be correctly processed. | | | +===================+ | ! "Model Unit" ! | D_receive ---! conversions !--- A_signal | ! provided by !--- A_pcref | D_enable --->! model author !--- A_gcref | ! ! | +===================+ | Model Unit consists only of AMS code | (a_gnd and a_extref are not shown) | | Figure 5: AMS Model Unit, using an I/O buffer as an example | | | +===================================================+ | ! "Model Unit" +-------+! | ! +--------+ | |! | D_receive --!-<| A_to_D |--< (analog receive ports) --<| |!-- A_puref | ! +--------+ | |! | ! | |!-- A_pdref | ! +--------+ | SPICE |! | D_drive --!->| D_to_A |--> (analog drive ports) -->| code |!-- A_signal | ! +--------+ | |! | ! | |!-- A_pcref | ! +--------+ | |! | D_enable --!->| D_to_A |--> (analog enable ports) -->| |!-- A_gcref | ! +--------+ | |! | ! +-------+! | +===================================================+ | Model Unit consists of SPICE code plus A_to_D and D_TO_A converters | (references for D_to_A and A_to_D converters not shown) | | Figure 6: SPICE Model Unit, using an I/O buffer as an example | |============================================================================= with: |** SPICE, VHDL-A(MS), Verilog-A(MS) versus VHDL-AMS and VERILOG-AMS |** |** SPICE, VHDL-A(MS), Verilog-A(MS) cannot process digital signals. All |** SPICE, VHDL-A(MS), Verilog-A(MS) input and output signals must be in analog |** format. Consequently, IBIS multi-lingual models using SPICE, VHDL-A(MS) or |** Verilog-A(MS) require analog-to-digital (A_to_D) and/or digital-to-analog | (D_to_A) converters to be provided by the EDA tool. The converter | subparameters are declared by the user, as part of the [External Model] or | [External Circuit] syntax, with user-defined names for the ports which |** connect the converters to the analog ports of the SPICE, VHDL-A(MS), |** or Verilog-A(MS) model. The details behind these declarations are | explained in the keyword definitions below. | | To summarize, Verilog-AMS and VHDL-AMS contain all the capability needed to | ensure that a model unit consists of only digital ports and/or analog ports. |** SPICE, VHDL-A(MS) and Verilog-A(MS), however, need extra data conversion, | provided by the EDA tool, to ensure that any digital signals can be | correctly processed. | | |* +===================+ |* | "Model Unit" | |* D_receive ---<| AMS code |--- A_puref |* | D_to_A and A_to_D |--- A_pdref |* D_drive --->| conversions |--- A_signal |* | provided by |--- A_pcref |* D_enable --->| model author |--- A_gcref |* | | |* +===================+ |* Model Unit consists only of AMS code |* (a_gnd and a_extref are not shown) |* |* Figure 5: AMS Model Unit, using an I/O buffer as an example | | | |* +==================================================+ |* | "Model Unit" +--------+| |* | +--------+ | || |* D_receive --|-<| A_to_D |--<(analog receive ports)--<| ||-- A_puref |* | +--------+ | A pure || |* | | analog ||-- A_pdref |* | +--------+ | I/O || |* D_drive --|->| D_to_A |-->(analog drive ports) -->| buffer ||-- A_signal |* | +--------+ | model || |* | | ||-- A_pcref |* | +--------+ | || |* D_enable --|->| D_to_A |-->(analog enable ports) -->| ||-- A_gcref |* | +--------+ | || |* | +--------+| |* +==================================================+ |** Model Unit consists of SPICE, VHDL-A(MS), Verilog-A(MS) code plus |** A_to_D and D_TO_A converters |* (references for D_to_A and A_to_D converters not shown) |* |* Figure 6: An analog-only Model Unit, using an I/O buffer as an example | |============================================================================= Under the keywords [External Model], [End External Model], replace: | Language: | | Accepts "SPICE", "VHDL-AMS", or "Verilog-AMS" as arguments. | The Language subparameter is required and must appear only | once. with: | Language: | |* Accepts "SPICE", "VHDL-AMS", "Verilog-AMS", "VHDL-A(MS)" |* or "Verilog-A(MS)" as arguments. The Language subparameter | is required and must appear only once. In the same keyword section, under "Parameter" change 2nd paragraph from: | Parameter passing is not supported in SPICE. VHDL-AMS | parameters are supported using "generic" names, and | Verilog-AMS parameters are supported using "parameter" names. to: |* Parameter passing is not supported in SPICE. VHDL-AMS and |* VHDL-A(MS) parameters are supported using "generic" names, and |* Verilog-AMS and Verilog-A(MS) parameters are supported using |* "parameter" names. In the same keyword section, under "Ports" change 2nd paragraph from: | Note that the user may connect | SPICE models to A_to_D and D_to_A converters using custom | names for analog ports within the model unit, so long as the | digital ports of the converters use the digital reserved port | names. to: | Note that the user may connect |* SPICE, Verilog-A(MS) and VHDL-A(MS) models to A_to_D and D_to_A converters using custom | names for analog ports within the model unit, so long as the | digital ports of the converters use the digital reserved port | names. Under section "Digital-to-Analog/Analog-to-Digital Conversions", replace: | These subparameters define all digital-to-analog and | analog-to-digital converters needed to properly connect | digital signals with the analog ports of referenced external | SPICE models. These subparameters must be used when [External | Model] references a file written in the SPICE language. They | are not permitted with Verilog-AMS or VHDL-AMS external files. with: | These subparameters define all digital-to-analog and | analog-to-digital converters needed to properly connect | digital signals with the analog ports of referenced external |* SPICE, Verilog-A(MS) or VHDL-A(MS) models. These subparameters must be used when [External |* Model] references a file written in the SPICE, Verilog-A(MS) or VHDL-A(MS) languages. They | are not permitted with Verilog-AMS or VHDL-AMS external files. Under section "D_to_A", replace: | As assumed in [Model], some interface ports of [External | Model] circuits expect digital input signals. As SPICE models | understand only analog signals, some conversion from digital | to analog format is required. with: | As assumed in [Model], some interface ports of [External |* Model] circuits expect digital input signals. As SPICE, Verilog-A(MS) or VHDL-A(MS) models | understand only analog signals, some conversion from digital | to analog format is required. A couple of paragraphs down in the same section also replace: | The port1 and port2 entries hold the SPICE analog | input port names across which voltages are specified. These with: |* The port1 and port2 entries hold the SPICE, Verilog-A(MS) or VHDL-A(MS) analog | input port names across which voltages are specified. These Under section "A_to_D", replace: | The A_to_D subparameter is used to generate a digital state | ('0', '1', or 'X') based on analog voltages generated by the | SPICE model or analog voltages present at the pad/pin. This | allows an analog signal from the external SPICE circuit or | pad/pin to be read as a digital signal by the simulation tool. with: | The A_to_D subparameter is used to generate a digital state | ('0', '1', or 'X') based on analog voltages generated by the |* SPICE, Verilog-A(MS) or VHDL-A(MS) model or analog voltages present at the pad/pin. This |* allows an analog signal from the external SPICE, Verilog-A(MS) or VHDL-A(MS) circuit or | pad/pin to be read as a digital signal by the simulation tool. Above Figure 7, replace: | Note that, while the port assignments and SPICE model must | be provided by the user, the D_to_A and A_to_D converters will | be provided automatically by the tool (the converter | parameters must still be declared by the user). There is no | need for the user to develop external SPICE code specifically | for these functions. | | A conceptual diagram of the port connections of a SPICE | [External Model] is shown below. with: |* Note that, while the port assignments and a SPICE, Verilog-A(MS) or VHDL-A(MS) model must | be provided by the user, the D_to_A and A_to_D converters will | be provided automatically by the tool (the converter | parameters must still be declared by the user). There is no |* need for the user to develop external SPICE, Verilog-A(MS) or VHDL-A(MS) code specifically | for these functions. | |* A conceptual diagram of the port connections of a SPICE, Verilog-A(MS) or VHDL-A(MS) | [External Model] is shown below. Change Figure 7 and its caption from: | +-------------+ | | | | +------------+ | |--- A_puref | | |>--- my_drive ---->| | | D_drive -->| D_to_A | | | | | |---- my_ref -------| |--- A_pdref | +------------+ | | | | | | +------------+ | [External |--- A_pcref | | |>--- my_enable --->| Model] | | D_enable -->| D_to_A | | using | | | |---- A_gcref ------| SPICE |--- A_gcref | +------------+ | | | | | | +------------+ | |--- A_signal | | |<--- my_receive --<| | | D_receive -<| A_to_D | | | | | |---- my_ref -------| |--- A_extref | +------------+ | | | A_gnd ---| | | +-------------+ | | Figure 7: Example of an [External Model] I/O buffer using SPICE to: |* +--------------+ |* | | |* +------------+ | |--- A_puref |* | |>--- my_drive ---->| | |* D_drive -->| D_to_A | | | |* | |---- my_ref -------| |--- A_pdref |* +------------+ | | |* | | |* +------------+ | [External |--- A_pcref |* | |>--- my_enable --->| Model] | |* D_enable -->| D_to_A | | using | |* | |---- A_gcref ------| SPICE, |--- A_gcref |* +------------+ |Verilog-A(MS),| |* | or | |* +------------+ | VHDL-A(MS) |--- A_signal |* | |<--- my_receive --<| | |* D_receive -<| A_to_D | | | |* | |---- my_ref -------| |--- A_extref |* +------------+ | | |* A_gnd ---| | |* +--------------+ |* |* Figure 7: Example of an [External Model] I/O buffer using SPICE, Verilog-A(MS) or VHDL-A(MS) Under section "Pseudo-Differential Buffers", replace: | The D_to_A adapters used for SPICE files can be set up to | control ports on pseudo-differential buffers. If SPICE is | used as an external language, the [Diff Pin] vdiff | subparameter overrides the contents of vlow and vhigh under | A_to_D. | | IMPORTANT: For pseudo-differential buffers under [External | Model], the analog input response may only be measured at the | die pads. The [Diff Pin] parameter is required, and controls | both the polarity and the differential thresholds used to | determine the D_receive port response (the D_receive port will | follow the state of the non-inverting pin/pad as referenced | to the inverting pin/pad). For SPICE models, the A_to_D line | must name the A_signal port under either port1 or port2, as | with a single-ended buffer. with: |* The D_to_A adapters used for SPICE, Verilog-A(MS) or VHDL-A(MS) files can be set up to |* control ports on pseudo-differential buffers. If SPICE, Verilog-A(MS) or VHDL-A(MS) is | used as an external language, the [Diff Pin] vdiff | subparameter overrides the contents of vlow and vhigh under | A_to_D. | | IMPORTANT: For pseudo-differential buffers under [External | Model], the analog input response may only be measured at the | die pads. The [Diff Pin] parameter is required, and controls | both the polarity and the differential thresholds used to | determine the D_receive port response (the D_receive port will | follow the state of the non-inverting pin/pad as referenced |* to the inverting pin/pad). For SPICE, Verilog-A(MS) or VHDL-A(MS) models, the A_to_D line | must name the A_signal port under either port1 or port2, as | with a single-ended buffer. Change the caption of Figure 8 from: | Figure 8 - Example SPICE implementation to: | Figure 8 - Example SPICE, Verilog-A(MS) or VHDL-A(MS) implementation Change the text above Figure 11 from: | The D_to_A or A_to_D adapters used for SPICE files may be set | up to control or respond to true differential ports. An | example is shown below. to: |* The D_to_A or A_to_D adapters used for SPICE, Verilog-A(MS) or VHDL-A(MS) files may be set | up to control or respond to true differential ports. An | example is shown below. Change the caption of Figure 11 from: | Figure 11: Example SPICE, Verilog-A(MS) or VHDL-A(MS) implementation of a true differential buffer In the 1st paragraph below Figure 11, replace: | If at-pad or at-pin measurement using a SPICE [External Model] | is desired, the vlow and vhigh entries under the A_to_D | subparameter must be consistent with the values of the [Diff | Pin] vdiff subparameter entry (the vlow value must match | -vdiff, and the vhigh value must match +vdiff). The logic with: |* If at-pad or at-pin measurement using a SPICE, Verilog-A(MS) or VHDL-A(MS) [External Model] | is desired, the vlow and vhigh entries under the A_to_D | subparameter must be consistent with the values of the [Diff | Pin] vdiff subparameter entry (the vlow value must match | -vdiff, and the vhigh value must match +vdiff). In the 2nd paragraph below Figure 11, replace: | IMPORTANT: For true-differential buffers under [External | Model], the user can choose whether to measure the analog | input response at the die pads or internal to the circuit | (this does not preclude tools from reporting digital D_receive | and/or analog responses in addition to at-pad A_signal | response). If at-pad measurements for a SPICE model are | desired, the A_signal_pos port would be named in the A_to_D | line under port1 and A_signal_neg under port2. with: | IMPORTANT: For true-differential buffers under [External | Model], the user can choose whether to measure the analog | input response at the die pads or internal to the circuit | (this does not preclude tools from reporting digital D_receive | and/or analog responses in addition to at-pad A_signal |* response). If at-pad measurements for a SPICE, Verilog-A(MS) or VHDL-A(MS) model are | desired, the A_signal_pos port would be named in the A_to_D | line under port1 and A_signal_neg under port2. In the 5th paragraph below Figure 11, replace: | For both SPICE and *-AMS true differential [External Model]s, | the EDA tool must not override or change the model author's | connection of the D_receive port. with: |* For SPICE, Verilog-A(MS) or VHDL-A(MS) and *-AMS true differential [External Model]s, | the EDA tool must not override or change the model author's | connection of the D_receive port. Under section "Series and Series Switch Models", replace: | As with other digital ports, the use of | SPICE in an [External Model] requires the user to declare | D_to_A ports, to convert the D_switch signal to an analog | input to the SPICE model (whether the port's state may | actually change during a simulation is determined by the EDA | tool used). with: | As with other digital ports, the use of |* SPICE, Verilog-A(MS) or VHDL-A(MS) in an [External Model] requires the user to declare | D_to_A ports, to convert the D_switch signal to an analog |* input to the SPICE, Verilog-A(MS) or VHDL-A(MS) model (whether the port's state may | actually change during a simulation is determined by the EDA | tool used). Add the following two examples after the 3rd example under the [External Model] keyword section: |**------------------------------------------- |** Example [External Model] using VHDL-A(MS): |**------------------------------------------- |** **[Model] ExBufferVHDL_analog **Model_type I/O **Vinh = 2.0 **Vinl = 0.8 |** |** Other model subparameters are optional |** |** typ min max **[Voltage Range] 3.3 3.0 3.6 |** **[Ramp] **dV/dt_r 1.57/0.36n 1.44/0.57n 1.73/0.28n **dV/dt_f 1.57/0.35n 1.46/0.44n 1.68/0.28n |** **[External Model] **Language VHDL-A(MS) |** |** Corner corner_name file_name circuit_name entity(architecture) **Corner Typ buffer_typ.vhd buffer(buffer_io_typ) **Corner Min buffer_min.vhd buffer(buffer_io_min) **Corner Max buffer_max.vhd buffer(buffer_io_max) |** |** Parameters List of parameters **Parameters delay rate **Parameters preemphasis |** |** Ports List of port names (in same order as in VHDL-A(MS)) **Ports A_signal my_drive my_enable my_receive my_ref **Ports A_puref A_pdref A_pcref A_gcref A_extref |** |** D_to_A d_port port1 port2 vlow vhigh trise tfall corner_name **D_to_A D_drive my_drive my_ref 0.0 3.3 0.5n 0.3n Typ **D_to_A D_enable my_enable A_gcref 0.0 3.3 0.5n 0.3n Typ |** |** A_to_D d_port port1 port2 vlow vhigh corner_name **A_to_D D_receive my_receive my_ref 0.8 2.0 Typ |** |** Note: A_signal might also be used instead of a user-defined interface port |** for measurements taken at the die pads |** |**---------------------------------------------- |** Example [External Model] using Verilog-A(MS): |**---------------------------------------------- |** **[Model] ExBufferVerilog_analog **Model_type I/O **Vinh = 2.0 **Vinl = 0.8 |** |** Other model subparameters are optional |** |** typ min max **[Voltage Range] 3.3 3.0 3.6 |** **[Ramp] **dV/dt_r 1.57/0.36n 1.44/0.57n 1.73/0.28n **dV/dt_f 1.57/0.35n 1.46/0.44n 1.68/0.28n |** **[External Model] **Language Verilog-A(MS) |** |** Corner corner_name file_name circuit_name (module) **Corner Typ buffer_typ.va buffer_io_typ **Corner Min buffer_min.va buffer_io_min **Corner Max buffer_max.va buffer_io_max |** |** Parameters List of parameters **Parameters delay rate **Parameters preemphasis |** |** Ports List of port names (in same order as in Verilog-A(MS)) **Ports A_signal my_drive my_enable my_receive my_ref **Ports A_puref A_pdref A_pcref A_gcref A_extref |** |** D_to_A d_port port1 port2 vlow vhigh trise tfall corner_name **D_to_A D_drive my_drive my_ref 0.0 3.3 0.5n 0.3n Typ **D_to_A D_enable my_enable A_gcref 0.0 3.3 0.5n 0.3n Typ |** |** A_to_D d_port port1 port2 vlow vhigh corner_name **A_to_D D_receive my_receive my_ref 0.8 2.0 Typ |** |** Note: A_signal might also be used instead of a user-defined interface port |** for measurements taken at the die pads |** **[End External Model] |**-------------------------------------------- Under the keywords [External Circuit], [End External Circuit], replace: | Language: | | Accepts "SPICE", "VHDL-AMS", or "Verilog-AMS" as arguments. | The Language subparameter is required and may appear only | once. with: | Language: | |* Accepts "SPICE", "VHDL-AMS", "Verilog-AMS", "VHDL-A(MS)" |* or "Verilog-A(MS)" as arguments. The Language subparameter | is required and must appear only once. In the same keyword section, under "Parameter" change 2nd paragraph from: | Parameter passing is not supported in SPICE. VHDL-AMS | parameters are supported using "generic" names, and | Verilog-AMS parameters are supported using "parameter" names. to: |* Parameter passing is not supported in SPICE. VHDL-AMS and |* VHDL-A(MS) parameters are supported using "generic" names, and |* Verilog-AMS and Verilog-A(MS) parameters are supported using |* "parameter" names. In the "Digital-to-Analog/Analog-to-Digital Conversions" replace: | These subparameters define all digital-to-analog and | analog-to-digital converters needed to properly connect | digital signals with the analog ports of referenced external | SPICE models. These subparameters must be used when [External | Circuit] references a file written in the SPICE language. | They are not permitted with Verilog-AMS or VHDL-AMS external | files. with: | These subparameters define all digital-to-analog and | analog-to-digital converters needed to properly connect | digital signals with the analog ports of referenced external |* SPICE, Verilog-A(MS) or VHDL-A(MS) models. These subparameters must be used when [External |* Circuit] references a file written in the SPICE, Verilog-A(MS) or VHDL-A(MS) language. | They are not permitted with Verilog-AMS or VHDL-AMS external | files. Under section "D_to_A" replace: | As assumed in [Model] and [External Model], some interface | ports of [External Circuit]s expect digital input signals. As | SPICE models understand only analog signals, some conversion | from digital to analog format is required. with: | As assumed in [Model] and [External Model], some interface | ports of [External Circuit]s expect digital input signals. As |* SPICE, Verilog-A(MS) or VHDL-A(MS) models understand only analog signals, some conversion | from digital to analog format is required. A couple of paragraphs down in the same section also replace: | The port1 and port2 | entries hold the SPICE analog input port names across which | voltages are specified. with: | The port1 and port2 |* entries hold the SPICE, Verilog-A(MS) or VHDL-A(MS) analog input port names across which | voltages are specified. Under section "A_to_D" replace: | The A_to_D subparameter is used to generate a digital state | ('0', '1', or 'X') based on analog voltages from the SPICE | model or from the pad/pin. This allows an analog signal from | the external SPICE circuit to be read as a digital signal by | the simulation tool. with: | The A_to_D subparameter is used to generate a digital state |* ('0', '1', or 'X') based on analog voltages from the SPICE, Verilog-A(MS) or VHDL-A(MS) | model or from the pad/pin. This allows an analog signal from |* the external SPICE, Verilog-A(MS) or VHDL-A(MS) circuit to be read as a digital signal by | the simulation tool. A number of paragraphs down in the same section also replace: | Note that, while the port assignments and SPICE model data | must be provided by the user, the D_to_A and A_to_D converters | will be provided automatically by the tool. There is no need | for the user to develop external SPICE code specifically for | these functions. with: |* Note that, while the port assignments and SPICE, Verilog-A(MS) or VHDL-A(MS) model data | must be provided by the user, the D_to_A and A_to_D converters | will be provided automatically by the tool. There is no need |* for the user to develop external SPICE, Verilog-A(MS) or VHDL-A(MS) code specifically for | these functions. ****************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION Increasing number of EDA tool vendors are starting to support the Verilog-A language in their simulators. Most of these offerings implement the analog subset of the Verilog-AMS LRM. Since there is nothing to prevent someone from writing *-AMS models using only the analog subset of the language(s), it would be very desirable to let the [External Model] and [External Circuit] keywords accept such models in IBIS. ***************************************************************************** ANY OTHER BACKGROUND INFORMATION: This version of the BIRD includes a change to BIRD91.3 to make it consistent with the content of this BIRD. In addition, two examples have been added to illustrate the usage of these two "languages". Therefore BIRD100.2 (this version) is considered complete by the authors. BIRD100.1 is based on the current IBIS v4.1 specification and does not take into consideration any other BIRDs which may have since made any changes to Section 6b. A careful study is still in order to make the recommendations outlined in this BIRD comply with these BIRDs. Also, some adding some examples may be useful to illustrate the new concepts of using the analog only Verilog-A(MS) and VHDL-A(MS) models with the [External Model] and [External Circuit] keywords. ******************************************************************************