====================================================================== IBIS FUTURES/COOKBOOK SUBCOMMITTEE MEETING MINUTES Date: July 29, 2004 Attendees: Cadence Design Systems - Lance Wang Cisco - Vinu Arumugham, Syed Huq, Zhiping Yang Green Streak Programs - Lynne Green Intel - Michael Mirmak, Arpad Muranyi Mentor Graphics - John Angulo, Ian Dodd, Steve Kaufer, Yuriy Shlepnev Sun Microsystems - Istvan Novak Teraspeed Consulting - Bob Ross Xilinx - Mark Alexander ====================================================================== Next Meeting: Thursday, August 12 1 PM - 3 PM US Pacific Time Telephone Bridge Passcode 916-356-2663 1 977-8350 Agenda: 1 - 1:05 PM Opens 1:05 - 2 PM Cookbook Discussion - Review of initial Cookbook draft 2 - 2:15 PM Futures Discussion - Proper RLGC and Frequency-dependence treatment 2:15 - 3 PM Open Discussion Upcoming Meetings: Aug. 26 - Power integrity status checkpoint Sept. 9 - Touchstone(R) and Mathworks' AMP ======================================================================== COOKBOOK MINUTES Michael Mirmak reviewed the status of the cookbook and solicited suggestions for the next steps in revision. John Angulo observed that, as the proposed technical writer is not familiar with IBIS, the team would best start with creating their own first draft. Bob Ross added that Intel had driven the first and second versions of the original cookbook. Bob further suggested that one person should guide the writing process, exerting influence over style and content. John noted that he still had yet to contribute the differential flow section of the updated cookbook. Michael accepted the AR to create a new, reference draft of the 4.0 cookbook, by editing the 2.1 version and adding skeleton text for the missing sections. He will distribute this text before the next meeting. ======================================================================== FUTURES MINUTES Michael inquired about issues related to the current ICM IIRDs distributed for private review, stating that an ICM 1.1 draft could be closed for changes within the next few weeks. John commented that the only major issues were the content fixes from IIRD2 and the [End ICM Section] text string problem. Bob further noted that the 10 ohm matrix example inexplicably used scientific notation. Michael accepted the AR to check with Kelly Gren on the parser treatment of [End ICM Section] and stated that the requirement could be removed in IIRD4. He also agreed to update the on-line draft with a format similar to Bob's on the IBIS WIP drafts. John Angulo inquired about the treatment of [Row] under IIRD3, asking why non-numeric, non-ordered lsits were used in IBIS. Bob responded that this was useful in IBIS where an implicit mapping of pin names to ports exists, but was needlessly complicated for ICM, which is more general. John suggested that ICM 1.1 include a swathing eample. Further, Bob proposed adding Y and Z parameter Touchstone(R) support. Finally, Michael suggested that ICM 1.1 be prepared for ANSI balloting. Lynne inquired whether having ICM 1.1 and the IBIS specification as the same ballot would be useful, though Bob disagreed. Syed began the discussion of I-t curves and buffer/core power analyses by summarizing the progress so far. Power integrity represents a problem for device modeling, both at the buffer and core levels. Ji Ping noted that the industry trends toward higher currents, lower voltages and lower voltage margins mean that power issues have a larger impact on system performance. Presently, I/O noise tends to be part of timing budgets as SSO noise, though simulation of these effects is hindered by long simulation times and convergence issues. An IBIS-like approach in this area would help. Syed added that, from the core level, not a lot of information is available and published device specifications are ususally the only data that can be used in platform design. Bob Ross inquired about the methods used for simulating decoupling caps. Ian added that deciding where to place these caps is one of the key issues, with ideal vs. non-ideal plane modeling being another hinge factor in design. Core activity is also crucial in system power simulations. Mark Alexander inquired whether one can start with an I/O solution and work toward a core power modeling solution. Bob reviewed the history and approach of IBIS V-t curves, stating that I-t I/O power information is already present in the IBIS specification. Ian suggested that this information assumes perfect supplies, absent supply bounce; John added that power supply "sag" is also omitted in the usual IBIS treatment, including the resulting slew rate degradation. Ian also suggested that the number of buffers switching and their respective slew rates are required for accurate SSO simulations. Syed posed the fundamental question: should IBIS add the missing SSO data at an I/O level or attempt a complete core-level power modeling solution. Bob Suggested that SPICE or ICEM would be more appropriate, as these technologies model common nodes of interest more than the IBIS approach would permit. Syed disagreed, stating that SPICE is weakened by the issues noted above, and that Verilog/VHDL would be more appropriate for the core. The participants agreed that the assumption of perfect planes would need to be removed from any future modeling approach; this would prevent simply adding I-t tables to IBIS or another behavioral modeling approach. At a minimum, the participants agreed that any solution would require the following components: - the stimulus used on the system during data extraction - how many devices switching simultaneously and with what drive characteristics - V-t data for power and ground planes - data on sensitivity of the V-t tables to droop - crowbar current data vs. time - details of poewr structure (package parasitics, at a minimum) Participants agreed that SPICE might be adequate for I/O modeling purposes, but would become unwieldy for core power. VHDL-AMS or Verilog-AMS would be more appropriate, but would add complexity to validation. At present, a Kelvin resistor is often used to validate power behaviors, by measuring current vs. time through the resistor at the I/O pins. Jiang further suggested that Georgia Tech had pioneered a similar procedure for characterizing core switching profiles, outlined at EPEP. Bob suggested that ICEM already included impedance descriptions for frequency-domain models of structures for EMI modeling purposes, under a separate IBIS-like tool set. Jiang observed that all these approaches still omit pre-dirver current. Syed suggested partitioning the problem into an SSO solution, at the buffer (IBIS) level and an core solution using ICEM. He took the AR to come into a future meeting with a more concrete set of modeling proposals.