====================================================================== IBIS FUTURES/COOKBOOK SUBCOMMITTEE MEETING MINUTES Date: August 18, 2005 Attendees: ---------- Cadence Design Systems - Lance Wang, Shangli Wu Cisco - Zhiping Yang, Vinu Arumugham Intel - Michael Mirmak, Arpad Muranyi Green Streak Programs - Lynne Green Mentor Graphics - John Angulo, Ian Dodd Teraspeed - Bob Ross ====================================================================== Next Meeting: Thursday, August 25 9 AM - 11 AM US Pacific Time Telephone Bridge Passcode 916-356-2663 4 342-7682 Agenda: 9 - 9:05 AM Opens 9:05 - 9:15 AM Cookbook Checkpoint 9:15 - 10:20 AM Futures Discussion: BIRD95 - Test case status - Plans for Vote 10:20 - 11:00 AM Futures Discussion: BIRD100 Draft ======================================================================== FUTURES --------- The Futures meeting was again entirely devoted to BIRD95 discussion. Zhiping Yang summarized Lance Wang's, Syed Huq's and Zhiping's own positions from recent e-mails (note that Lance expressed disagreement in response to some of Syed's e-mail comments) 1) What kind of model should be used for BIRD95 method validation? Zhiping suggested a 130 nm or better device should be used, to include pre-driver and on-die parasitic information. BIRD95 cannot address gate modulation today. All other effects are second order or even third order effects once gate modulation is excluded. One BIRD cannot solve all power integrity problems, so we should keep BIRD95 as first-order effect coverage. 2) On the package model, what nodes and what current information should be included? In IBIS, power, ground and I/O are three nodes used for KCL calculation. Real circuits involve more nodes, which would complicate the BIRD95 approach. Zhiping recommends NOT putting circuit elements on ground side. 3) What are limitations on BIRD95? Zhiping reiterated that we should only address first-order effects. Lance asked what the BIRD is intended to cover in terms of real designs? We can stay limited on kinds of models, buffers, structures, etc. but it's hard to make assumptions about the people using the BIRD and for what purposes. Do we want to accept a limitation on our results that the BIRD95 enabled model must be EXACTLY like the original design? Lance noted that Cadence is performing lots of tests, and that IBIS by itself is not doing well. Unexpected results are coming out from BIRD95, which Cadence cannot explain. Zhiping responded, noting several issues about the test case and conditions: 1) Buffer type - the test buffer itself does not have on-die parasitics and lacks a predriver. Improvements from BIRD95 may not be significant. If on-die decouplng exists or there is significant predriver, results would be better. Zhiping's sense is that BIRD95 will not make things worse. 2) Quiet line - two parts: one part is the path to power, Vddq; the other is to ground. The way you split the C_comp from power to ground is critical. A small offset in power noise causes big effects on I/O, due to distortion. 3) Cadence buffer issue is shared by everyone - we are all looking for a publicly-available buffer to analyze and share. Last Friday, according to Lance, Micron provided an SDRAM, SSTL-2 buffer model for analysis. Michael Mirmak noted that Intel is working internally on distributing a relatively recent model for analysis. Zhiping reiterated the need for permission to test and publish the results publicly. Michael asked why 130 nm is the gold standard. Zhiping stated that it ensures a more complicated pre-driver circuit due to extra transistors needed to drive the I/O. Bob Ross followed up by asking why we assume that older technologies won't correlate to our BIRD95 method. In other words, an older model with fewer effects should correlate better under BIRD95 than a newer one. Bob continued by strongly demanding a 1:1 correlation between BIRD95 simulation and transistor-level data before approving the BIRD95 method. John Angulo added that, if the buffer voltage supply starts to sag, we are deviating from measurement conditions. Zhiping agreed, noting that the I-T tables are extracted under ideal conditions. He added that the sources for current in I-T tables include: 1) predriver 2) IO pin 3) crossbar and that the KCL calculations assume zero-summation of these currents. If no predriver exists in the model, then (2) and (3) are only sources of current. BUT if you deviate from the target voltage conditions, (2) and (3) will change. An approximation is possible, but only to the first-order. Bob agreed that approximation is the only thing possible. Zhiping suggests that three curves, IBIS, IBIS+BIRD95 and transistor should be enough for comparison. Lance mentioned Antonio Girardi's gate modulation work. The results are worse with I-T tables, because the tables data is "too strong." Zhiping responded that BIRD95 does NOT separate pre-driver currents from anything else; the BIRD95 I-T table is TOTAL current, not just pre-driver current. The last stage plus pre-driver current is based on IBIS sim conditions. Separation of pre-driver current is implemented on existing methods/versions of BIRD95. Lance countered that the procedure for separation of I-T table data is suspect. Michael asked about two issues: 1) Are we confident of the BIRD95 method as such? 2) Is the method complete (in other words, are second-order effects really second-order; do we cope well with the sag condition)? Lance noted that Cadence trusts Cisco's data and simply wants to know the limitations on the model and its validity. John recommended, for the sag condition, that data be extracted at 1.8 V, again at 2.0 V and again at 1.6 V. Good improvement should be noted when pre-driver effects are there, to a first-order approximation, independent of load, plus parasitics. Lynne Green raised the question of publishing results. When we can get to the point of releasing the data. For example, for the Micron models, would it be easier to have Randy as lead author to publish the models? Releasing the process models is very, very sensitive to all semiconductor manufacturers. Lance noted that Cadence wants to see quiet line test results. Zhiping responded that Cisco is very willing to include it for the next test cases. He added that a good test approach would use an ideal supply, then add AC noise to see whether IBIS and SPICE models correlate. Arpad Muranyi asked Lance how the presentation waveforms were generated? Were the buffer links to ideal ground removed? Lance noted that few differences were observed with the buffer corrections. Arpad disagreed, stating that a non-ideal ground reference for the substrate would result in a different gate capacitance than if we used ideal 0. Bob noted that we should ensure no confusion between "VDDQ" and "ZVDDQ" in our discussions. Zhiping agreed and noted that the major contribution of ZVDDQ is to dampen noise on the power supply rails. He added that R vs. T may be a more valid correlation condition for IBIS than I vs. T. Bob suggested that, in general, we ensure that the return paths are properly added in and that our I/O load DOESN'T corrupt that path. COOKBOOK --------- John Angulo suggested that readers might become confused by the wording on clamp adjustment procedures, particularly for Vcc-relative or Vcc-connected terminations. The wording doesn't capture what we're trying to do. He recommended adding an extra step in the adjustment procedures to clarify the process. Bob stated that, in general, he believes all curve extraction and analysis should be done ground-relative, followed by "a lot of" mathematical manipulation. Arpad and Michael both disagreed that this manipulation is easy to do, particularly for newer IBIS users. Michael will make adjustments to the text and provide it to the committee.