====================================================================== IBIS FUTURES/COOKBOOK SUBCOMMITTEE MEETING MINUTES Date: August 25, 2005 Attendees: ---------- Cadence Design Systems - Shangli Wu Cisco - Zhiping Yang, Vinu Arumugham Intel - Michael Mirmak, Arpad Muranyi Mentor Graphics - John Angulo, Ian Dodd NCSU - Ambrish Varma Sigrity - Sam Chitwood Teraspeed - Bob Ross ====================================================================== Next Meeting: Thursday, September 1, 2005 9 AM - 11 AM US Pacific Time Telephone Bridge Passcode 916-356-2663 3 505-8440 Agenda: 9 - 9:05 AM Opens 9:05 - 9:15 AM Cookbook Checkpoint 9:15 - 10:15 AM Futures Discussion: BIRD95 - BIRD95 Micron Data from Cisco (Zhiping) - Removal of Ground Parasitics (Zhiping) - Power Parasitics References (Ambrish) 10:15 - 11:00 AM Futures Discussion: BIRD100 Draft ======================================================================== COOKBOOK --------- John Angulo, Arpad Muranyi and Bob Ross have no problem with the termination adjustment sections. The non-termination adjustment generated some discussion regarding "should." Bob suggested altering the text to recommend extending the current values if the clamp has zero slope but extrapolating if a non-zero slope is seen. Michael Mirmak will make the changes and send out the new text for review. FUTURES --------- The Futures meeting was entirely devoted to BIRD95 discussion. Michael asked whether the Micron model was in use by the members. Zhiping Yang responded that Cisco would prefer to wait until Micron approves public release of the results. Michael will check into this with Randy Wolff. Bob observed that, for simulations, users need an equivalent Z network around the model plus I-T tables actually extracted from the original circuit. Ambrish Varma added that we do not yet have a step-by-step procedure for how BIRD95 extraction and comparison should be implemented. We only have a presentation as guidance. Zhiping stated that a more detailed implementation of BIRD95 is noted in his IEEE paper, including load-dependent I-T tables. The paper does not cover splitting of C_comp. John noted that the paper also does not cover quiet lines, parasitics on ground side and similar issues. Ambrish added that he has read at least a dozen papers which include parasitic information on the ground pin. To just discount having noise on the ground pin may be incorrect. Sam Chitwood recommended that the best way to perform power/ground analysis is to combine everything (all parasitics) into a loop. Include self- AND mututal inductances in this loop. If users want to use partials in power and ground, they run into trouble with mututals that relate those partials. The easiest way to avoid making a mistake is to use the loop concept to keep everything referenced to a single reference node. Voltage reference measurements are easier in this scenario. Even IBIS RLC package models can make sense when used with ideal node zero, if you put all the parasitics in the power side. Ambrish responded with a question: do we expect to see just a straight line at the ground node in such a case? Sam disagreed, noting that any voltage measurement needs two points: the measurement point and a reference. Ian Dodd expressed disagreement with three of Sam's statements. Item 1: A diff probe can take measurements with regard to a single reference point for an entire system if you use coaxial cables of the same length for both sides. Item 2: IBIS RLC package data makes no assumption of an artificial "ideal 0: ground. The RLC just a mutual plus a single L and single C. Item 3: Sticking a single path RLC for a single channel is OK. This does not work for more than one driver, due to shared components. These are separate but shared in a different way between different drivers. Sam responded that simulation analysis often comes down to what package information do you have. Typical customers for Sigrity are package designers performing SSO analysis to optimize their package designs. Solving 3D models directly by connecting package models to their IBIS drivers is their usual option. The standard will have to involve cases where this information is NOT available; recall that most IBIS users are board users. Normal customers find geting all the single and mutual effects correct very difficult. Ian suggested this might not work for advanced design. Ambrish asked about lumping everything together in the ground path versus the power path. Sam noted that he is not advocating "lumping everything together." The easiest way to think about this case is through using a single power/ground connection to the entire system. Ian suggested that multiple loops mess up the assumptions of a single loop. Sam agreed. Ian suggests some tools now have an SSN aspects, analyzing more than one driver at a time. Sam predicted that package houses will soon provide S-parameters to express power/ground paths. Michael added that s-parameter references no longer have physical meaning. So long as this is kept in mind, noise can be minimized through optimization. The voltage difference at input transistor at the receiver is the critical parameters. Sam agreed. Michael asked whether can we select/mandate a physical reference point for BIRD95. Sam responded that this would be tricky. Most transistor users have only two points to analyze, but some have full on-die models, which makes referencing very, very difficult. Ambrish suggested always taking ground 0 as the common node, taking signal measurements between ground and power pin. Pretty much everything is floating when the PCB is "ringing like hell" -- even the plane under the IC is at a different voltage relative to the PCB. Ambrish will compile several papers which show proper treatment of ground and power parasitics. Zhiping proposed that non-ideal power/ground models be allowed, but IBIS will not correlate to SPICE if parasitics are in the ground pins. Ambrish disagreed; Bernhard Unger has several presentations which show in-ground parasitics. Should we limit BIRD95 in some way relative to in-ground parasitics? Zhiping suggests problem with IBIS might exist because of this. Sam noted that BIRD95 is trying to develop a model for the silicon's behavior by itself. ZVDDQ is the parasitic of the silicon itself, not anything else. Zhiping made two requests: 1) can someone send the web link for Micron model 2) can we get confirmation that we do not have ideal node zero in the Micron model. Is it simplified? Does it have on-die and pre-driver? Ambrish asked about test cases; a quiet line with ideal ground does not settle anything. Do we need a quiet line test case at all? Arpad responded that, if a quiet line was analyzed with the driver output high, noise could come through on power supply rail. Sam observed that everything is referenced in proper analysis to a single node. When the driver goes low, the output shorts out the pulldown transistor. If you try to measure the voltage, you get zero. Measuring at the receiver, rather than output at driver, for quiet line is the proper method. Arpad suggested measuring a quiet line to voltage half-way between Vcc and ground. From a discussion with Antonio Girardi, when a quiet line drives low, you will not see current through pulldown (shorted). A resistive load to 1/2*Vcc will show some pulldown current.. If you have noise in the power/ground path and the gate voltage is not constant, the drive strength will change due to noise. Noise on the output is no longer constant. Michael asked, rhetorically, where the resistors were connected Where is the signal measured? Sam responded that noise at the receiver is the only criterion. Arpad asked about a specific application of "lumping it all together" in the power rail: what if your driver bounces 10 V but the receiver is quiet? How is the analysis affected. Sam responded that using S-parameters can prevent confusion. Michael agreed and gave an example. Bob inquired whether the team needs to settle the parasitics discussion to make progress with BIRD95. Even a 50% improvement over IBIS alone would be significant progress. He agreed with Sam that package model is a separate and highly complex issue. Shangli Wu expressed disagreement with the suggestion that if IBIS cannot handle a particular case then the silicon corresponding to that case should be excluded from treatment. Any test case should be a "black box." Shangli suggested that Cadence put power and ground probes in place around the test circuit and see what the differences are in SPICE, IBIS and IBIS+BIRD95 cases.