[IBIS Ver] 7.0 [File Name] memory_package.ibs [Date] 02/11/2014 [File Rev] 1.3 [Source] Randy Wolf, Walter Katz and Arpad Muranyi | [Notes] Revision History: Rev 1.0: 02/11/2014 | [Disclaimer] This IBIS File is an exemplar of IBIS files supplied by Micron, Inc. It is intended to be used to explain the types of package models that Micron, Inc. would like to deliver when IBIS-ISS package models are approved. | |*************************************************************************** | [Component] memory_package | [Package] | typ min max R_pkg 200.0m 200.0m 200.0m L_pkg 1.0nH 1.0nH 1.0nH C_pkg 0.5pF 0.5pF 0.5pF | [Pin] signal_name model_name R_pin L_pin C_pin A1 VDD POWER A2 VSSQ GND A3 NF NF_INPUT 200.0m 1.0nH 00 0.5pF A7 NF NF_INPUT 200.0m 1.0nH 00 0.5pF A8 VSSQ GND A9 VSS GND B1 VPP POWER B2 VDDQ POWER B3 DQS_c DQS 200.0m 1.0nH 00 0.5pF B7 DQ1 DQ 200.0m 1.0nH 00 0.5pF B8 VDDQ POWER B9 ZQ NC C1 VDDQ POWER C2 DQ0 DQ 200.0m 1.0nH 00 0.5pF C3 DQS_t DQS 200.0m 1.0nH 00 0.5pF C7 VDD POWER C8 VSS GND C9 VDDQ POWER D1 VSSQ GND D2 NC NC D3 DQ2 DQ 200.0m 1.0nH 00 0.5pF D7 DQ3 DQ 200.0m 1.0nH 00 0.5pF D8 NC NC D9 VSSQ GND E1 VSSL GND E2 VDDQ POWER E3 NC NC E7 NC NC E8 VDDQ POWER E9 VSS GND F1 VDDL POWER F2 NC NC F3 ODT INPUT 200.0m 1.0nH 00 0.5pF F7 CK_t CLKIN 200.0m 1.0nH 00 0.5pF F8 CK_c CLKIN 200.0m 1.0nH 00 0.5pF F9 VDD POWER G1 VSS GND G2 NC NC G3 CKE INPUT 200.0m 1.0nH 00 0.5pF G7 CS_n INPUT 200.0m 1.0nH 00 0.5pF G8 NC NC G9 RFU NC H1 VDD POWER H2 WE_n_A14 INPUT 200.0m 1.0nH 00 0.5pF H3 ACT_n INPUT 200.0m 1.0nH 00 0.5pF H7 CAS_n_A15 INPUT 200.0m 1.0nH 00 0.5pF H8 RAS_n INPUT 200.0m 1.0nH 00 0.5pF H9 VSS GND J1 VREFCA POWER J2 BG0 INPUT 200.0m 1.0nH 00 0.5pF J3 A10 INPUT 200.0m 1.0nH 00 0.5pF J7 A12_BC_n INPUT 200.0m 1.0nH 00 0.5pF J8 BG1 INPUT 200.0m 1.0nH 00 0.5pF J9 VDD POWER K1 VSS GND K2 BA0 INPUT 200.0m 1.0nH 00 0.5pF K3 A4 INPUT 200.0m 1.0nH 00 0.5pF K7 A3 INPUT 200.0m 1.0nH 00 0.5pF K8 BA1 INPUT 200.0m 1.0nH 00 0.5pF K9 VSS GND L1 RESET_n RESET 200.0m 1.0nH 00 0.5pF L2 A6 INPUT 200.0m 1.0nH 00 0.5pF L3 A0 INPUT 200.0m 1.0nH 00 0.5pF L7 A1 INPUT 200.0m 1.0nH 00 0.5pF L8 A5 INPUT 200.0m 1.0nH 00 0.5pF L9 ALERT_n ALERT 200.0m 1.0nH 00 0.5pF M1 VDD POWER M2 A8 INPUT 200.0m 1.0nH 00 0.5pF M3 A2 INPUT 200.0m 1.0nH 00 0.5pF M7 A9 INPUT 200.0m 1.0nH 00 0.5pF M8 A7 INPUT 200.0m 1.0nH 00 0.5pF M9 VPP POWER N1 VSS GND N2 A11 INPUT 200.0m 1.0nH 00 0.5pF N3 PARITY INPUT 200.0m 1.0nH 00 0.5pF N7 NC NC N8 A13 INPUT 200.0m 1.0nH 00 0.5pF N9 VDD POWER | |*************************************************************************** | Possible keyword names for a new keyword which would be used to define | bus names in which only signal pins are mentioned: | [Buffer Supply Terminals] | [Bus Mapping] |*************************************************************************** |****************************PIN MAPPING************************************ | [Pin Mapping] pulldown_ref pullup_ref gnd_clamp_ref power_clamp_ref ext_ref A1 NC VDD A2 VSSQ NC A3 NC NC VSSQ VDDQ A7 NC NC VSSQ VDDQ A8 VSSQ NC A9 VSS NC B1 NC VPP B2 NC VDDQ B3 VSSQ VDDQ VSSQ VDDQ B7 VSSQ VDDQ VSSQ VDDQ B8 NC VDDQ B9 NC NC C1 NC VDDQ C2 VSSQ VDDQ VSSQ VDDQ C3 VSSQ VDDQ VSSQ VDDQ C7 NC VDD C8 VSS NC C9 NC VDDQ D1 VSSQ NC D2 NC NC D3 VSSQ VDDQ VSSQ VDDQ D7 VSSQ VDDQ VSSQ VDDQ D8 NC NC D9 VSSQ NC E1 VSSL NC E2 NC VDDQ E3 NC NC E7 NC NC E8 NC VDDQ E9 VSS NC F1 NC VDDL F2 NC NC F3 NC NC VSS VDD F7 NC NC VSS VDD F8 NC NC VSS VDD F9 NC VDD G1 VSS NC G2 NC NC G3 NC NC VSS VDD G7 NC NC VSS VDD G8 NC NC G9 NC NC H1 NC VDD H2 NC NC VSS VDD H3 NC NC VSS VDD H7 NC NC VSS VDD H8 NC NC VSS VDD H9 VSS NC J1 NC VREFCA J2 NC NC VSS VDD J3 NC NC VSS VDD J7 NC NC VSS VDD J8 NC NC VSS VDD J9 NC VDD K1 VSS NC K2 NC NC VSS VDD K3 NC NC VSS VDD K7 NC NC VSS VDD K8 NC NC VSS VDD K9 VSS NC L1 NC NC VSS VDD L2 NC NC VSS VDD L3 NC NC VSS VDD L7 NC NC VSS VDD L8 NC NC VSS VDD L9 VSS VDDQ VSS VDDQ M1 NC VDD M2 NC NC VSS VDD M3 NC NC VSS VDD M7 NC NC VSS VDD M8 NC NC VSS VDD M9 NC VPP N1 VSS NC N2 NC NC VSS VDD N3 NC NC VSS VDD N7 NC NC N8 NC NC VSS VDD N9 NC VDD | |**********************DIFF PIN********************************************* [Diff_pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max | C3 B3 0.000V 0ns NA NA F7 F8 0.250V 0ns NA NA | |*************************************************************************** |*************************************************************************** | SiSoft: |*************************************************************************** | [Die Supply Pads] VDD1 VDD VDD2 VDD VDD3 VDD VSS1 VSS VSS2 VSS VSS3 VSS VSSQ VSSQ VDDQ VDDQ VSSQ VSSQ [End Die Supply Pads] | |*************************************************************************** | BIRD 163-165: |*************************************************************************** | [Node Declarations] pad_vdd1 pad_vdd2 pad_vdd3 pad_vss1 pad_vss2 pad_vss3 pad_vddq pad_vssq [End Node Declarations] | |*************************************************************************** | SiSoft: |*************************************************************************** | [Begin ISS Model] IO | This model uses all I/O pins. There are ports for each I/O pin and it's buffer Language Touchstone File Value io.s76p Ports Pin.A3 Pin.A7 Pin.B3 Pin.B7 Pin.C2 Pin.C3 Pin.D3 Pin.D7 Pin.F3 Pin.N8 Ports Pin.F7 Pin.F8 Pin.G3 Pin.G7 Pin.H2 Pin.H3 Pin.H7 Pin.H8 Pin.J2 Pin.J3 Ports Pin.J7 Pin.J8 Pin.K2 Pin.K3 Pin.K7 Pin.K8 Pin.L1 Pin.L2 Pin.L3 Pin.L7 Ports Pin.L8 Pin.L9 Pin.M2 Pin.M3 Pin.M7 Pin.M8 Pin.N2 Pin.N3 Ports Buf.A3 Buf.A7 Buf.B3 Buf.B7 Buf.C2 Buf.C3 Buf.D3 Buf.D7 Buf.F3 Buf.N8 Ports Buf.F7 Buf.F8 Buf.G3 Buf.G7 Buf.H2 Buf.H3 Buf.H7 Buf.H8 Buf.J2 Buf.J3 Ports Buf.J7 Buf.J8 Buf.K2 Buf.K3 Buf.K7 Buf.K8 Buf.L1 Buf.L2 Buf.L3 Buf.L7 Ports Buf.L8 Buf.L9 Buf.M2 Buf.M3 Buf.M7 Buf.M8 Buf.N2 Buf.N3 [End ISS Model] | |*************************************************************************** | BIRD 163-165: |*************************************************************************** | [Circuit Call] IO_PKG Parameters TS_FileName = "Rx_Typ.s76p" | mapping port pin/pad/node Port_map 1 A3 Port_map 2 A7 Port_map 3 B3 Port_map 4 B7 Port_map 5 C2 Port_map 6 C3 Port_map 7 D3 Port_map 8 D7 Port_map 9 F3 Port_map 10 N8 Port_map 11 F7 Port_map 12 F8 Port_map 13 G3 Port_map 14 G7 Port_map 15 H2 Port_map 16 H3 Port_map 17 H7 Port_map 18 H8 Port_map 19 J2 Port_map 20 J3 Port_map 21 J7 Port_map 22 J8 Port_map 23 K2 Port_map 24 K3 Port_map 25 K7 Port_map 26 K8 Port_map 27 L1 Port_map 28 L2 Port_map 29 L3 Port_map 30 L7 Port_map 31 L8 Port_map 32 L9 Port_map 33 M2 Port_map 34 M3 Port_map 35 M7 Port_map 36 M8 Port_map 37 N2 Port_map 38 N3 | Port_map 39 signal:A3 Port_map 40 signal:A7 Port_map 41 signal:B3 Port_map 42 signal:B7 Port_map 43 signal:C2 Port_map 44 signal:C3 Port_map 45 signal:D3 Port_map 46 signal:D7 Port_map 47 signal:F3 Port_map 48 signal:N8 Port_map 49 signal:F7 Port_map 50 signal:F8 Port_map 51 signal:G3 Port_map 52 signal:G7 Port_map 53 signal:H2 Port_map 54 signal:H3 Port_map 55 signal:H7 Port_map 56 signal:H8 Port_map 57 signal:J2 Port_map 58 signal:J3 Port_map 59 signal:J7 Port_map 60 signal:J8 Port_map 61 signal:K2 Port_map 62 signal:K3 Port_map 63 signal:K7 Port_map 64 signal:K8 Port_map 65 signal:L1 Port_map 66 signal:L2 Port_map 67 signal:L3 Port_map 68 signal:L7 Port_map 69 signal:L8 Port_map 70 signal:L9 Port_map 71 signal:M2 Port_map 72 signal:M3 Port_map 73 signal:M7 Port_map 74 signal:M8 Port_map 75 signal:N2 Port_map 76 signal:N3 [End Circuit Call] | |*************************************************************************** | SiSoft: |*************************************************************************** | [Begin ISS Model] Power_One_Die_Node_Per_Rail | This model uses package subckt One_Per_Rail, with 10pf on-die capacitiance for this silicon | Ports are all of the Power and GND pins, and one port for each on-die voltage Language IBIS-ISS File Value One_Per_Rail.iss Subckt Value One_Per_Rail Parameter Value Cdie_VDD Value 10pf Parameter Value Cdie_VDDQ Value 4f Ports Pin.A1 Pin.A2 Pin.A8 Pin.A9 Pin.B2 Pin.B8 Pin.C1 Pin.C7 Pin.C8 Pin.C9 Pin.D1 Pin.E2 Ports Pin.E8 Pin.E9 Pin.F9 Pin.G1 Pin.H1 Pin.H9 Pin.J9 Pin.K1 Pin.K9 Pin.M1 Pin.N1 Pin.N9 Ports Buf_Sig.VSSQ Buf_Sig.VSS Buf_Sig.VDD Buf_Sig.VDDQ [End ISS Model] | |*************************************************************************** | BIRD 163-165: |*************************************************************************** | [Circuit Call] Power_One_Die_Node_Per_Rail Parameters TS_FileName = "Rx_Typ.s28p" | mapping port pin/pad/node Port_map 1 A1 Port_map 2 A2 Port_map 3 A8 Port_map 4 A9 Port_map 5 B2 Port_map 6 B8 Port_map 7 C1 Port_map 8 C7 Port_map 9 C8 Port_map 10 C9 Port_map 11 D1 Port_map 12 E2 Port_map 13 E8 Port_map 14 E9 Port_map 15 F9 Port_map 16 G1 Port_map 17 H1 Port_map 18 H9 Port_map 19 J9 Port_map 20 K1 Port_map 21 K9 Port_map 22 M1 Port_map 23 N1 Port_map 24 N9 Port_map 25 power_bus:VSSQ Port_map 26 power_bus:VSS Port_map 27 power_bus:VDD Port_map 28 power_bus:VDDQ [End Circuit Call] | |*************************************************************************** | SiSoft: |*************************************************************************** | | Other flavors of PDN Modeling | | Ports are all of the Power and GND pins, PUR and PDR (or PCR and GCR) ports for each buffer | [Begin ISS Model] Power_One_Die_Node_Per_Buffer Language IBIS-ISS File Value One_Per_Buffer.iss Subckt Value One_Per_Buffer Ports Pin.A1 Pin.A2 Pin.A8 Pin.A9 Pin.B2 Pin.B8 Pin.C1 Pin.C7 Pin.C8 Pin.C9 Pin.D1 Pin.E2 Ports Pin.E8 Pin.E9 Pin.F9 Pin.G1 Pin.H1 Pin.H9 Pin.J9 Pin.K1 Pin.K9 Pin.M1 Pin.N1 Pin.N9 Ports Buf_GCR.A3 Buf_PCR.A3 Buf_GCR.A7 Buf_PCR.A7 Buf_PDR.B3 Buf_PUR.B3 Buf_PDR.B7 Buf_PUR.B7 Ports Buf_PDR.C2 Buf_PUR.C2 Buf_PDR.C3 Buf_PUR.C3 Buf_PDR.D3 Buf_PUR.D3 Buf_PDR.D7 Buf_PUR.D7 Ports Buf_GCR.F3 Buf_PCR.F3 Buf_GCR.F7 Buf_PCR.F7 Buf_GCR.F8 Buf_PCR.F8 Buf_GCR.G3 Buf_PCR.G3 Ports Buf_GCR.G7 Buf_PCR.G7 Buf_GCR.H2 Buf_PCR.H2 Buf_GCR.H3 Buf_PCR.H3 Buf_GCR.H7 Buf_PCR.H7 Ports Buf_GCR.H8 Buf_PCR.H8 Buf_GCR.J2 Buf_PCR.J2 Buf_GCR.J3 Buf_PCR.J3 Buf_GCR.J7 Buf_PCR.J7 Ports Buf_GCR.J8 Buf_PCR.J8 Buf_GCR.K2 Buf_PCR.K2 Buf_GCR.K3 Buf_PCR.K3 Buf_GCR.K7 Buf_PCR.K7 Ports Buf_GCR.K8 Buf_PCR.K8 Buf_GCR.L1 Buf_PCR.L1 Buf_GCR.L2 Buf_PCR.L2 Buf_GCR.L3 Buf_PCR.L3 Ports Buf_GCR.L7 Buf_PCR.L7 Buf_GCR.L8 Buf_PCR.L8 Buf_PDR.L9 Buf_PUR.L9 Buf_GCR.M2 Buf_PCR.M2 Ports Buf_GCR.M3 Buf_PCR.M3 Buf_GCR.M7 Buf_PCR.M7 Buf_GCR.M8 Buf_PCR.M8 Buf_GCR.N2 Buf_PCR.N2 Ports Buf_GCR.N3 Buf_PCR.N3 Buf_GCR.N8 Buf_PCR.N8 [End ISS Model] | |*************************************************************************** | BIRD 163-165: |*************************************************************************** | [Circuit Call] Power_One_Die_Node_Per_Buffer Parameters TS_FileName = "Rx_Typ.s100p" | mapping port pin/pad/node Port_map 1 A1 Port_map 2 A2 Port_map 3 A8 Port_map 4 A9 Port_map 5 B2 Port_map 6 B8 Port_map 7 C1 Port_map 8 C7 Port_map 9 C8 Port_map 10 C9 Port_map 11 D1 Port_map 12 E2 Port_map 13 E8 Port_map 14 E9 Port_map 15 F9 Port_map 16 G1 Port_map 17 H1 Port_map 18 H9 Port_map 19 J9 Port_map 20 K1 Port_map 21 K9 Port_map 22 M1 Port_map 23 N1 Port_map 24 N9 Port_map 25 gcref:A3 Port_map 26 pcref:A3 Port_map 27 gcref:A7 Port_map 28 pcref:A7 Port_map 29 gcref:B3 Port_map 30 pcref:B3 Port_map 31 gcref:B7 Port_map 32 pcref:B7 Port_map 33 pdref:C2 Port_map 34 puref:C2 Port_map 35 pdref:C3 Port_map 36 puref:C3 Port_map 37 pdref:D3 Port_map 38 puref:D3 Port_map 39 pdref:D7 Port_map 40 puref:D7 Port_map 41 gcref:F3 Port_map 42 pcref:F3 Port_map 43 gcref:F7 Port_map 44 pcref:F7 Port_map 45 gcref:F8 Port_map 46 pcref:F8 Port_map 47 gcref:G3 Port_map 48 pcref:G3 Port_map 49 gcref:G7 Port_map 50 pcref:G7 Port_map 51 gcref:H2 Port_map 52 pcref:H2 Port_map 53 gcref:H3 Port_map 54 pcref:H3 Port_map 55 gcref:H7 Port_map 56 pcref:H7 ... [End Circuit Call] | |*************************************************************************** | SiSoft: |*************************************************************************** | [Begin ISS Model] Package_One_Die_Node_Per_Buffer | Ports are all of the Power and GND die pads, PUR and PDR (or PCR and GCR) ports for each buffer Language IBIS-ISS File Value Package_One_Per_Buffer.iss Subckt Value Package_One_Per_Buffer Ports Pad.VDD1 Pad.VDD2 Pad.VDD3 Pad.VSS1 Pad.VSS2 Pad.VSS3 Pad.VSSQ Pad.VDDQ Pad.VSSQ Ports Pin.A1 Pin.A2 Pin.A8 Pin.A9 Pin.B2 Pin.B8 Pin.C1 Pin.C7 Pin.C8 Pin.C9 Pin.D1 Pin.E2 Ports Pin.E8 Pin.E9 Pin.F9 Pin.G1 Pin.H1 Pin.H9 Pin.J9 Pin.K1 Pin.K9 Pin.M1 Pin.N1 Pin.N9 [End ISS Model] | [Begin ISS Model] Die_One_Die_Node_Per_Buffer | Ports are all of the Power and GND die pads, PUR and PDR port for each buffer Language IBIS-ISS File Value Die_One_Per_Buffer.iss Subckt Value Die_One_Per_Buffer Ports Pad.VDD1 Pad.VDD2 Pad.VDD3 Pad.VSS1 Pad.VSS2 Pad.VSS3 Pad.VSSQ Pad.VDDQ Pad.VSSQ Ports Buf_GCR.A3 Buf_PCR.A3 Buf_GCR.A7 Buf_PCR.A7 Buf_PDR.B3 Buf_PUR.B3 Buf_PDR.B7 Buf_PUR.B7 Ports Buf_PDR.C2 Buf_PUR.C2 Buf_PDR.C3 Buf_PUR.C3 Buf_PDR.D3 Buf_PUR.D3 Buf_PDR.D7 Buf_PUR.D7 Ports Buf_GCR.F3 Buf_PCR.F3 Buf_GCR.F7 Buf_PCR.F7 Buf_GCR.F8 Buf_PCR.F8 Buf_GCR.G3 Buf_PCR.G3 Ports Buf_GCR.G7 Buf_PCR.G7 Buf_GCR.H2 Buf_PCR.H2 Buf_GCR.H3 Buf_PCR.H3 Buf_GCR.H7 Buf_PCR.H7 Ports Buf_GCR.H8 Buf_PCR.H8 Buf_GCR.J2 Buf_PCR.J2 Buf_GCR.J3 Buf_PCR.J3 Buf_GCR.J7 Buf_PCR.J7 Ports Buf_GCR.J8 Buf_PCR.J8 Buf_GCR.K2 Buf_PCR.K2 Buf_GCR.K3 Buf_PCR.K3 Buf_GCR.K7 Buf_PCR.K7 Ports Buf_GCR.K8 Buf_PCR.K8 Buf_GCR.L1 Buf_PCR.L1 Buf_GCR.L2 Buf_PCR.L2 Buf_GCR.L3 Buf_PCR.L3 Ports Buf_GCR.L7 Buf_PCR.L7 Buf_GCR.L8 Buf_PCR.L8 Buf_PDR.L9 Buf_PUR.L9 Buf_GCR.M2 Buf_PCR.M2 Ports Buf_GCR.M3 Buf_PCR.M3 Buf_GCR.M7 Buf_PCR.M7 Buf_GCR.M8 Buf_PCR.M8 Buf_GCR.N2 Buf_PCR.N2 Ports Buf_GCR.N3 Buf_PCR.N3 Buf_GCR.N8 Buf_PCR.N8 [End ISS Model] | |*************************************************************************** | BIRD 163-165: |*************************************************************************** | [Circuit Call] Package_One_Die_Node_Per_Buffer Parameters TS_FileName = "Rx_Typ.s33p" | mapping port pin/pad/node Port_map 1 pad_vdd1 Port_map 2 pad_vdd2 Port_map 3 pad_vdd3 Port_map 4 pad_vss1 Port_map 5 pad_vss2 Port_map 6 pad_vss3 Port_map 7 pad_vddq Port_map 8 pad_vssq Port_map 9 A1 Port_map 11 A2 Port_map 12 A8 Port_map 13 A9 Port_map 14 B2 Port_map 15 B8 Port_map 16 C1 Port_map 17 C7 Port_map 18 C8 Port_map 19 C9 Port_map 20 D1 Port_map 21 E2 Port_map 22 E8 Port_map 23 E9 Port_map 24 F9 Port_map 25 G1 Port_map 26 H1 Port_map 27 H9 Port_map 28 J9 Port_map 29 K1 Port_map 30 K9 Port_map 31 M1 Port_map 32 N1 Port_map 33 N9 [End Circuit Call] | | [Circuit Call] Die_One_Die_Node_Per_Buffer Parameters TS_FileName = "Rx_Typ.s85p" | mapping port pin/pad/node Port_map 1 pad_vdd1 Port_map 2 pad_vdd2 Port_map 3 pad_vdd3 Port_map 4 pad_vss1 Port_map 5 pad_vss2 Port_map 6 pad_vss3 Port_map 7 pad_vddq Port_map 8 pad_vssq Port_map 9 gcref:A3 Port_map 10 pcref:A3 Port_map 11 gcref:A7 Port_map 12 pcref:A7 Port_map 13 gcref:B3 Port_map 14 pcref:B3 Port_map 15 gcref:B7 Port_map 16 pcref:B7 Port_map 17 pdref:C2 Port_map 18 puref:C2 Port_map 19 pdref:C3 Port_map 20 puref:C3 Port_map 21 pdref:D3 Port_map 22 puref:D3 Port_map 23 pdref:D7 Port_map 24 puref:D7 Port_map 25 gcref:F3 Port_map 26 pcref:F3 Port_map 27 gcref:F7 Port_map 28 pcref:F7 Port_map 29 gcref:F8 Port_map 30 pcref:F8 Port_map 31 gcref:G3 Port_map 32 pcref:G3 Port_map 33 gcref:G7 Port_map 34 pcref:G7 Port_map 35 gcref:H2 Port_map 36 pcref:H2 Port_map 37 gcref:H3 Port_map 38 pcref:H3 Port_map 39 gcref:H7 Port_map 40 pcref:H7 ... [End Circuit Call] | |******************************************************************************** | [Model] Tx ... | [Model] Rx ... | |******************************************************************************** | [External Circuit] IO_PKG Package_model Language IBIS-ISS | Corner corner_name file_name circuit_name (.subckt name) Corner Typ Package.inc Package Ports 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Ports 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Ports 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 Ports 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 [End External Circuit] | | [External Circuit] Power_One_Die_Node_Per_Rail Package_model Language IBIS-ISS | Corner corner_name file_name circuit_name (.subckt name) Corner Typ Package.inc Package Ports 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Ports 15 16 17 18 19 20 21 22 23 24 25 26 27 28 [End External Circuit] | ... ... |******************************************************************************** | [End]