====================================================================== IBIS INTERCONNECT TASK GROUP http://www.ibis.org/interconnect_wip/ Mailing list: ibis-interconnect@freelists.org Archives at http://www.freelists.org/archive/ibis-interconn/ ====================================================================== Attendees from January 6 Meeting (* means attended at least using audio) ANSYS Curtis Clark* Cadence Design Systems Bradley Brim Cisco David Siadat Intel Corp. Michael Mirmak* Keysight Technologies Radek Biernacki Mentor Graphics Arpad Muranyi* Micron Technology Justin Butterfield*, Randy Wolff* SAE ITC Maureen Lemankiewicz, Logen Johnson Signal Integrity Software Walter Katz*, Mike LaBonte* Teraspeed Labs Bob Ross* University of Aveiro in Portugal Wael Dghais Agenda for Jan. 12, 2016 Review of Attendees Call for Patents Review of Previous Meeting Minutes: Jan. 6, 2016 Opens Review additional Interconnect Draft BIRD Drawings Review DesignCon presentation Review of Draft 28 (29, if available) Michael Mirmak convened the meeting. No patents were declared. Mike LaBonte moved to approve the minutes. Arpad Muranyi seconded the motion. The minutes were approved without objection. Bob Ross mentioned that he has comments on the team’s DesignCon Interconnect presentation plans. Mike reviewed an additional drawing, showing a 6-pin example, with several pads connected. Arpad raised concerns about POWER and GROUND comments in the final column. Mike and Walter Katz pointed out these are comments, not actual column information. The correct terminology should be “PU_REF”, “GC_REF”, etc. Separate package and die models are intended. Bob stated that the picture is more or less OK. The key point is that common interface at the rail is the *signal name*. Some verbiage still needed. Walter stated that, for this case, we don’t need two pads for VCC and two pads for VSS. Mike replied that there are many straight-through packages. Walter noted there are different pad names most likely, but this is trying to illustrate a different point. Arpad asked whether this isn’t trying to show one die terminal to two different pads? Walter responded that you would need Die Pad Names. Bob added that you don’t use the Die Pad Names in this case. Walter stated this is a very good example, but we have to change it a bit. Here, the person who generated the die model did so with one terminal for VSS and one for VDD. The package designer has two terminals on the die for each and therefore two connections for each. He therefore has to name those die pads on the package side; the terminals are therefore names by die pad name, and die supply pads are added. Bob noted that this was the whole point of his Interconnect presentation, admittedly going into very specific detail. Walter agreed, referring to his presentation from several weeks ago. We can connect by bus label, die pad, or pin name. 9 cases are possible. Mike stated that his drawing is small enough to show with text on a single page. Die pads and bus label corrections may be needed. For next time, corrections will be shown plus an example with signal and power split into separate circuits. Not trivial, but of interest, and would fit on a page. In terms of smaller corrections to the drawings, Bob noted that a model name must be used with [Begin Interconnect Model]. Curtis Clark observed that the package model doesn’t sync with the picture. The list of pins isn’t in the same order. Walter referred to his Oct. 17 mail regarding 9 cases and on-die models. Die Pads discussion Walter stated that Die Supply Pads, not Pin Pad Mapping, is preferred and reviewed a few key points. Signal names are Bus Labels – this is automatic. Power and Ground Bus Labels default to Signal Names as well. Walter showed a new Die Supply Pads section; this text should be used in Draft 29. Arpad asked whether we pick up bus labels in the final column. Walter noted that we have three pieces of information on a pin – its name, bus label, and [missed the third one]. For a particular I/O’s pull-up reference, we know its name and its Bus Label. We have enough information to associate the two. Mike raised concerns about overloaded use of “bus_label” as a phrase. Walter replied that the key IBIS assumption is that if two signals have the same signal_name, they must have the same model_name. You can’t have two signal names “VDD” where one connects to power and one connects to ground. This is the same assumption used for Bus Labels. Several other rules follow from this. Walter asked Bob about using Die Supply Pads vs. Pin Pad Mapping. Bob replied that, on the basis of many-to-one, we can use Die Supply Pads; the Pin-Pad Mapping proposal is withdrawn. Walter replied that a new section on Die Supply Pads belongs in the draft (slide 4 in presentation). Then the rules need to be scrubbed vs. the parser with a reference used on the Pullup_Ref on one instance and Pulldown_ref on another. Die Supply Pads are totally optional. Bob asked whether any DesignCon presentation will summarize previous presentation at EPEPS. Mike has action items to clarify some items. Bob may give a presentation to fill in other details missing here or hard to understand. Walter stated that he has updated/cleaned up the presentation but not yet done for the slides. He will e-mail it for team to review. Bob’s presentation focuses on pin rail and pad rail; Walter’s 9 cases are shown. Michael mentioned confusion might occur with this amount of detail without clear statement of principles for EDA vendors and model makers. Mike moved to adjourn. Arpad seconded. The meeting adjourned.