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IBIS INTERCONNECT TASK GROUP
http://www.ibis.org/interconnect_wip/ 
Mailing list: ibis-interconnect@freelists.org 
Archives at http://www.freelists.org/archive/ibis-interconn/ 

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Attendees from January 8, 2020 Meeting (* means attended at least using audio)

ANSYS                                Curtis Clark
Cadence Design Systems               Bradley Brim
Intel Corp.                          Michael Mirmak*
Keysight Technologies                Radek Biernacki
Mentor, A Siemens Business           Arpad Muranyi*
Micron Technology                    Justin Butterfield*, Randy Wolff*
SiSoft                               Walter Katz*, Mike LaBonte
Teraspeed Labs                       Bob Ross*


Michael Mirmak convened the meeting.  No patents were declared. 
Justin Butterfield took minutes.


Review of Minutes:
- Michael called for review of the minutes from the December 18, 2019 meeting. 
  Randy Wolff moved to approve the minutes.  Bob Ross seconded.  The minutes 
  were approved without objection.


Review of ARs: 
- Randy to look into a picture of DIMM routing for the EMD BIRD.
  - Randy reported he has started to look into this, but he would like to have 
    more discussion and gather some ideas on the best way to generate the 
	picture.
  
- Walter Katz to send out EMD draft 28.
  - Michael reported this is done.

   
Opens:
 - None.
 

EMD DIMM Pictures:
Randy stated his plan was to create a picture of an RDIMM routing to show the 
new EMD capabilities.  The intention is to show an internal net and extended 
net on the DIMM.  Randy noted he is having some difficulty simplifying the 
layout to only show the net of interest.  Michael suggested change the colors 
of the nets of interest and change the nets not of interest to match the 
background color.  Randy replied he can try this.  Randy noted he would like 
to show both external and internal interface nets.  Michael asked if he also 
wanted to show an extended net.  Randy stated he would like to include this 
and point to EMD concepts such as terminals.  Bob agreed with simplifying the 
layout shown in the picture as much as possible.

Bob asked, in the extended net case, if the resistor would be an IBIS file 
component.  Walter noted there are two approaches.  One is to have a separate 
set of interconnect models for each net in the extended net.  The other 
approach is to include the resistor value in one interconnect model for the 
complete extended net.  Michael suggested we could add some examples to show 
these cases based on the drawing.  Randy noted we could also have the case of 
a DC blocking capacitor forming the extended net.


EMD draft 28 review:
Walter noted Michael had made some comments and edits to the draft.  Randy 
also had a few comments and editorial fixes.  Michael stated, at the end of 
page 26, there is a term "bus_label_name".  Michael asked if we want to remove 
the second underscore to change the phrase to "bus_label name".  Randy 
suggested to change it to "rail bus_label name".  Bob had suggested to delete 
this paragraph.  Walter agreed with Randy's change.

Bob commented that there are technical details to resolve.  It is not clear 
which interconnect interface we are talking about in the rules.  Michael asked 
which section of the BIRD this applies to.  Walter agreed there are 
clarifications to be made, but he does not want to do a blanket change.  
Walter suggested to submit this draft to get a BIRD number then work on these 
details.  Bob gave an example of a pin that connects to itself, and asked how 
the syntax would handle this case.  Randy asked if we want to wait to get a 
BIRD number before Friday or before DesignCon.  Walter replied before 
DesignCon is his goal.  Bob noted there are several technical issues that need 
to be resolved.  

Michael noted changes to an existing paragraph on page 10.  There is a 
statement about connectivity, and he made some clarification changes to this.  
Walter stated that any pins with the same signal_name are connected.  Bob 
commented we need to be careful of connected vs. shorted.  Michael asked if we 
want to explicitly state they are not shorted.  And, he asked what are we 
trying to say when we say they are connected.  Bob noted power routing may be 
a different case to consider.  There are electrical connections between 
terminals, and the resistance should be included and not shorted out by the 
tool.  Michael asked if we need to define the points of connections to inform 
the user on the nets of interest, while shorts are assumed, and this is 
important information for the model user.

Randy noted the text in question is also on page 7.  Bob asked if this is 
talking about I/Os or rails.  Bob noted extended nets are not shorts.  Walter 
suggested we can delete the paragraph on page 10.  Walter noted nets can be 
connected but not shorted, while bus_labels define shorts.  Bob agreed the 
second paragraph on page 10 makes this more clear.

Michael will send out a draft 30 [AR].  

We will review the connectivity discussion and clean up the document for 
submission to the IBIS Open Forum in the next meeting.


Next Meeting:
The next meeting will be January 15.


Randy moved to adjourn.  Arpad Muranyi seconded.  The meeting adjourned without 
objection.

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Bin List:

EMD Comments to be Resolved:


IBIS-ISS Parser:
- IBIS-ISS parser scope document