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IBIS INTERCONNECT TASK GROUP
http://www.ibis.org/interconnect_wip/  
Mailing list: ibis-interconnect@freelists.org  
Archives at http://www.freelists.org/archive/ibis-interconn/  
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Attendees from February 3 Meeting (* means attended at least using audio)
ANSYS                                                                Curtis Clark*
Cadence Design Systems                              Bradley Brim
Cisco                                                                   David Siadat
Intel Corp.                                                         Michael Mirmak*
Keysight Technologies                                   Radek Biernacki
Mentor Graphics                                             Arpad Muranyi*
Micron Technology                                         Justin Butterfield*, Randy Wolff*
SAE ITC                                                               Maureen Lemankiewicz, Logen Johnson
Signal Integrity Software                               Walter Katz*, Mike LaBonte*
Teraspeed Labs                                                Bob Ross*
University of Aveiro in Portugal                  Wael Dghais
 
Michael Mirmak convened the meeting.  No patents were declared.   Mike LaBonte commented about minutes missing from the archive; these are being posted now (catching up from September 2015).  Mike LaBonte moved to approve the minutes as amended.   Bob Ross seconded the motion.  The minutes were approved without objection. 
 
Walter Katz showed his proposed [Pin Mapping] changes (this was sent to the distribution list).  Bus_label changes were of concern to Bob Ross.  POWER and GND (P/G) pins with the same signal_name are assumed connected.  Package interconnect models can have PCB terminal connections to POWER and GND pins, P/G bus labels, or P/G signal_names.  Michael asked about non-nodal connections; are these possible and do these represent virtual shorts?  Walter replied that direct terminal connections are shorts between pins in the package.   You can attach to a signal_name to attach to everything.  All connections have two handles: bus_label, signal_name.  However, you cannot have bus_labels and signal_names for VDD.
 
Bob will provide suggested changes to Walter’s text, in writing (AR Bob); this will be discussed in the meeting next week.  Walter noted that the change is not intended as a BIRD, but only as a BIDD (as discussed in the IBIS Summit).  Bob mentioned that, separately, there is a need to resolve how NC interacts with Pin Mapping.  Multi-lingual support and interaction is also a potential problem.  Circuit Call and External Circuit effects are limited in use with Pin Mapping, and are less impacted than External Model.  Mike suggested that there is also a need to check merged pins treatment in the specification.
 
No time remained to review the Draft 29 text.
 
For next time, the  Draft 29 text will be reviewed first.  Afterwards, the Pin Mapping treatment, including NC and other interactions, including Bob’s suggested changes, will be discussed.
 
Mike moved to adjourn.  Curtis Clark seconded the motion.  The meeting adjourned.