====================================================================== IBIS INTERCONNECT TASK GROUP http://www.ibis.org/interconnect_wip/ Mailing list: ibis-interconnect@freelists.org Archives at http://www.freelists.org/archive/ibis-interconn/ ====================================================================== Attendees from February 17 Meeting (* means attended at least using audio) ANSYS Curtis Clark* Cadence Design Systems Bradley Brim Cisco David Siadat Intel Corp. Michael Mirmak* Keysight Technologies Radek Biernacki Mentor Graphics Arpad Muranyi* Micron Technology Justin Butterfield*, Randy Wolff* SAE ITC Maureen Lemankiewicz, Logen Johnson Signal Integrity Software Walter Katz*, Mike LaBonte* Teraspeed Labs Bob Ross* University of Aveiro in Portugal Wael Dghais Michael Mirmak convened the meeting. No patents were declared. Randy Wolff moved to approve the minutes. Mike LaBonte seconded the motion. The minutes were approved without objections. Walter Katz summarized offline and reflector discussions – no terminal can be connected to two or more pins. The new rules can be summarized in three statements shown in his message of Tuesday, 2/16/2016. These will be integrated into Draft 30 of the Interconnect proposal draft. Walter noted that a question was raised regarding parser checking of these rules/relationships. Bob Ross and Walter came up with alternate algorithms. These will be considered to be normative. Bob suggested that examples of violations be provided as informative. Bob showed a terminal_type table explaining power and ground pins in relation to I/O pins. He also raised a concern about whether a terminal connected to a pullup_ref constitutes a violation or an override if accompanied by direct connections. He also highlighted some typographical issues with the proposal as written. Rules under Buffer Rail are a concern to Bob, as they suggest Pin is under Buffer Rail or part of a Buffer Rail choice. In the ports and terminals section of the proposal draft, Walter suggested modifying one sentence for clarification on port definitions. Michael continued the review of the draft proposal, in the terminal definition section. Some comments were raised several revisions ago regarding pre-PCB-layout vs. post-layout rules and whether the interconnect proposal only addressed one type. Walter replied that every file is to be assumed to be a post-layout file and a complete component. Michael added that a separate BIRD already exists on this, to be resolved after the Interconnect BIRD proposal is finalized. Bob asked for a change to the placement of Number_of_terminals rules. Michael asked whether the phrase “Aggressor” should appear in square brackets or curly brackets. Arpad Muranyi noted that reference connection does not carry current or signals, making the terminal section confusing on nodes vs. ports. Walter replied that a probe reference node is permitted to be itself. Michael asked whether this should be required. We have removed node 0 as an option. Walter replied that nothing stops an EDA tool from connecting this to a node 0. Arpad wants to allow ideal node 0 and perhaps not to even allow direct connection to POWER or GND. Arpad accepted an AR to define and explain the supported referencing schemes for the next meeting. Curtis Clark suggested that this is a two-conductor problem. The way it is currently written is correct for S-parameters, but perhaps not for W-elements or partial inductance representations (loop current issue). Walter noted that, in Touchstone, you can refer to references in two ways: using [Reference] or in the options line. Time did not allow in-depth discussion. For next time, Michael will prepare a Draft 30 for team review. A focus area for discussion will be the Terminal and node/port definitions. Curtis moved to adjourn the meeting. Bob seconded the motion. The meeting adjourned.